From: Andrey Miroshnikov Date: Thu, 10 Feb 2022 15:50:20 +0000 (+0000) Subject: Added optional reverse arg to send TDI data MSB-first X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d8bf21d37504d89537c397d32c84e772db5d3d37;p=soc.git Added optional reverse arg to send TDI data MSB-first --- diff --git a/src/soc/debug/test/test_jtag_tap.py b/src/soc/debug/test/test_jtag_tap.py index 3981904a..6c984ed3 100644 --- a/src/soc/debug/test/test_jtag_tap.py +++ b/src/soc/debug/test/test_jtag_tap.py @@ -25,11 +25,16 @@ def tms_state_set(dut, bits): yield yield dut.bus.tms.eq(0) +def tms_data_getset(dut, tms, d_len, d_in=0, reverse=False): + if reverse: + # Reverse the for loop to transmit MSB-first + bit_range = range(d_len-1, -1, -1) + else: + bit_range = range(d_len) -def tms_data_getset(dut, tms, d_len, d_in=0): res = 0 yield dut.bus.tms.eq(tms) - for i in range(d_len): + for i in bit_range: tdi = 1 if (d_in & (1<