From: Luke Kenneth Casson Leighton Date: Sun, 3 Apr 2022 10:29:33 +0000 (+0100) Subject: fix some of instantiation errors in opencores_ethmac.py X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=d982e1ef558d7d3d4b26b4108f1e01d59bf0663d;p=soc.git fix some of instantiation errors in opencores_ethmac.py --- diff --git a/src/soc/bus/opencores_ethmac.py b/src/soc/bus/opencores_ethmac.py index 3078fa67..5720c1ce 100644 --- a/src/soc/bus/opencores_ethmac.py +++ b/src/soc/bus/opencores_ethmac.py @@ -111,6 +111,7 @@ class EthMAC(Elaboratable): def elaborate(self, platform): m = Module() comb = m.d.comb + idx = self.idx # Calculate arbiter bus address wb_master_bus_adr = Signal(32) @@ -119,7 +120,6 @@ class EthMAC(Elaboratable): # create definition of external verilog EthMAC code here, so that # nmigen understands I/O directions (defined by i_ and o_ prefixes) - idx = self.idx ethmac = Instance("eth_top", # Clock/reset (use DomainRenamer if needed) i_wb_clk_i=ClockSignal(),