From: Raptor Engineering Development Team Date: Tue, 22 Feb 2022 18:35:30 +0000 (-0600) Subject: Extend LiteDRAM VHDL wrapper to allow more than one clock line X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ddc1cc062caed16cbc7fc948e973f4ad72b486f9;p=microwatt.git Extend LiteDRAM VHDL wrapper to allow more than one clock line This is necessary for the upcoming Arctic Tern system enablement --- diff --git a/core_dram_tb.vhdl b/core_dram_tb.vhdl index 7df3dfd..f65125a 100644 --- a/core_dram_tb.vhdl +++ b/core_dram_tb.vhdl @@ -121,6 +121,7 @@ begin DRAM_ABITS => 24, DRAM_ALINES => 1, DRAM_DLINES => 16, + DRAM_CKLINES => 1, DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => DRAM_INIT_FILE, PAYLOAD_SIZE => ROM_SIZE diff --git a/dram_tb.vhdl b/dram_tb.vhdl index 571bd70..ca7c90b 100644 --- a/dram_tb.vhdl +++ b/dram_tb.vhdl @@ -44,6 +44,7 @@ begin DRAM_ABITS => 24, DRAM_ALINES => 1, DRAM_DLINES => 16, + DRAM_CKLINES => 1, DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => DRAM_INIT_FILE, PAYLOAD_SIZE => DRAM_INIT_SIZE diff --git a/fpga/top-acorn-cle-215.vhdl b/fpga/top-acorn-cle-215.vhdl index bcbadad..9183125 100644 --- a/fpga/top-acorn-cle-215.vhdl +++ b/fpga/top-acorn-cle-215.vhdl @@ -272,6 +272,7 @@ begin DRAM_ABITS => 26, DRAM_ALINES => 16, DRAM_DLINES => 16, + DRAM_CKLINES => 1, DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE diff --git a/fpga/top-arty.vhdl b/fpga/top-arty.vhdl index 68d1e89..4125506 100644 --- a/fpga/top-arty.vhdl +++ b/fpga/top-arty.vhdl @@ -85,8 +85,8 @@ entity toplevel is ddram_dq : inout std_ulogic_vector(15 downto 0); ddram_dqs_p : inout std_ulogic_vector(1 downto 0); ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; + ddram_clk_p : out std_ulogic_vector(0 downto 0); + ddram_clk_n : out std_ulogic_vector(0 downto 0); ddram_cke : out std_ulogic; ddram_odt : out std_ulogic; ddram_reset_n : out std_ulogic @@ -346,6 +346,7 @@ begin DRAM_ABITS => 24, DRAM_ALINES => 14, DRAM_DLINES => 16, + DRAM_CKLINES => 1, DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE diff --git a/fpga/top-genesys2.vhdl b/fpga/top-genesys2.vhdl index fcd190f..fc1218e 100644 --- a/fpga/top-genesys2.vhdl +++ b/fpga/top-genesys2.vhdl @@ -275,6 +275,7 @@ begin DRAM_ABITS => 25, DRAM_ALINES => 15, DRAM_DLINES => 32, + DRAM_CKLINES => 1, DRAM_PORT_WIDTH => 256, PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE diff --git a/fpga/top-nexys-video.vhdl b/fpga/top-nexys-video.vhdl index 86bdd11..485b3a7 100644 --- a/fpga/top-nexys-video.vhdl +++ b/fpga/top-nexys-video.vhdl @@ -263,6 +263,7 @@ begin DRAM_ABITS => 25, DRAM_ALINES => 15, DRAM_DLINES => 16, + DRAM_CKLINES => 1, DRAM_PORT_WIDTH => 128, PAYLOAD_FILE => RAM_INIT_FILE, PAYLOAD_SIZE => PAYLOAD_SIZE diff --git a/litedram/extras/litedram-wrapper-l2.vhdl b/litedram/extras/litedram-wrapper-l2.vhdl index 5823f19..0923f6f 100644 --- a/litedram/extras/litedram-wrapper-l2.vhdl +++ b/litedram/extras/litedram-wrapper-l2.vhdl @@ -13,6 +13,7 @@ entity litedram_wrapper is DRAM_ABITS : positive; DRAM_ALINES : natural; DRAM_DLINES : natural; + DRAM_CKLINES : natural; DRAM_PORT_WIDTH : positive; -- Pseudo-ROM payload @@ -69,8 +70,8 @@ entity litedram_wrapper is ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0); ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; + ddram_clk_p : out std_ulogic_vector(DRAM_CKLINES-1 downto 0); + ddram_clk_n : out std_ulogic_vector(DRAM_CKLINES-1 downto 0); ddram_cke : out std_ulogic; ddram_odt : out std_ulogic; ddram_reset_n : out std_ulogic @@ -93,8 +94,8 @@ architecture behaviour of litedram_wrapper is ddram_dq : inout std_ulogic_vector(DRAM_DLINES-1 downto 0); ddram_dqs_p : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); ddram_dqs_n : inout std_ulogic_vector(DRAM_DLINES/8-1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; + ddram_clk_p : out std_ulogic_vector(DRAM_CKLINES-1 downto 0); + ddram_clk_n : out std_ulogic_vector(DRAM_CKLINES-1 downto 0); ddram_cke : out std_ulogic; ddram_odt : out std_ulogic; ddram_reset_n : out std_ulogic; diff --git a/litedram/extras/sim_litedram.vhdl b/litedram/extras/sim_litedram.vhdl index 0016240..295c111 100644 --- a/litedram/extras/sim_litedram.vhdl +++ b/litedram/extras/sim_litedram.vhdl @@ -102,8 +102,8 @@ entity litedram_core is ddram_dq : inout std_ulogic_vector(15 downto 0); ddram_dqs_p : inout std_ulogic_vector(1 downto 0); ddram_dqs_n : inout std_ulogic_vector(1 downto 0); - ddram_clk_p : out std_ulogic; - ddram_clk_n : out std_ulogic; + ddram_clk_p : out std_ulogic_vector(0 downto 0); + ddram_clk_n : out std_ulogic_vector(0 downto 0); ddram_cke : out std_ulogic; ddram_odt : out std_ulogic; ddram_reset_n : out std_ulogic;