From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Sat, 9 Mar 2019 03:41:12 +0000 (-0800)
Subject: Add VectorAssembler to make the graph from yosys beautiful.
X-Git-Tag: div_pipeline~2334
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=df8bcf181f05ee20da67b48a18291978fa845854;p=soc.git

Add VectorAssembler to make the graph from yosys beautiful.
---

diff --git a/TLB/src/VectorAssembler.py b/TLB/src/VectorAssembler.py
new file mode 100644
index 00000000..517dc51e
--- /dev/null
+++ b/TLB/src/VectorAssembler.py
@@ -0,0 +1,20 @@
+from nmigen import Array, Module, Signal
+from nmigen.cli import main 
+
+class VectorAssembler():
+    def __init__(self, width):
+        # Internal
+        self.width = width
+        
+        # Input
+        self.input = Array(Signal(1) for index in range(width))
+        
+        # Output
+        self.o = Signal(width)
+        
+    def elaborate(self, platform=None):
+        m = Module()
+        for index in range(self.width):
+            m.d.comb += self.o[index].eq(self.input[index])
+            
+        return m
\ No newline at end of file
diff --git a/TLB/test/test_vector_assembler.py b/TLB/test/test_vector_assembler.py
new file mode 100644
index 00000000..8e07c9c7
--- /dev/null
+++ b/TLB/test/test_vector_assembler.py
@@ -0,0 +1,38 @@
+import sys
+sys.path.append("../src")
+sys.path.append("../../TestUtil")
+
+from nmigen.compat.sim import run_simulation
+
+from test_helper import assert_eq, assert_ne, assert_op
+from VectorAssembler import VectorAssembler
+
+assembler_size = 4
+
+def set_assembler(dut, input):
+    assert len(input) == assembler_size
+    for index in range(assembler_size):
+        input_index = assembler_size - index - 1
+        yield dut.input[index].eq(input[input_index])
+    yield
+    
+def check_output(dut, o, op):
+    out_o = yield dut.o
+    assert_op("Output", out_o, o, op)
+    
+
+def testbench(dut):
+    input = [1, 1, 0, 0]
+    output = 12
+    yield from set_assembler(dut, input)
+    yield from check_output(dut, output, 0)
+    
+    input = [1, 1, 0, 1]
+    output = 13
+    yield from set_assembler(dut, input)
+    yield from check_output(dut, output, 0)    
+
+if __name__ == "__main__":
+    dut = VectorAssembler(assembler_size)
+    run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_vector_assembler.vcd")
+    print("VectorAssembler Unit Test Success")
\ No newline at end of file