From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 24 Jan 2022 17:36:26 +0000 (+0000)
Subject: alter order of TAP.add_io() parameters to put src_loc_at last
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eb28aea69c7a785085364c2fb3c2cbdbe86f4890;p=c4m-jtag.git

alter order of TAP.add_io() parameters to put src_loc_at last
---

diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py
index 938c4fa..e0cf747 100755
--- a/c4m/nmigen/jtag/tap.py
+++ b/c4m/nmigen/jtag/tap.py
@@ -547,8 +547,9 @@ class TAP(Elaboratable):
                     dmi.we_i.eq(ds.ongoing("WRRD")),
                 ]
 
-    def add_io(self, *, iotype, name=None, src_loc_at=0,
-                                banksel=0, pullup=False, pulldown=False):
+    def add_io(self, *, iotype, name=None, banksel=0,
+                                pullup=False, pulldown=False,
+                                src_loc_at=0):
         """Add a io cell to the boundary scan chain
 
         Parameters:
@@ -749,7 +750,6 @@ class TAP(Elaboratable):
             # tdo = reg[0], tdo_en = shift
             tdos.append((reg[0], sr_shift))
 
-
         # Assign the right tdo to the bus tdo
         for i, (tdo, tdo_en) in enumerate(tdos):
             if i == 0:
@@ -766,7 +766,6 @@ class TAP(Elaboratable):
             # Always connect tdo_jtag to
             m.d.comb += self.bus.tdo.eq(tdo_jtag)
 
-
     def add_wishbone(self, *, ircodes, address_width, data_width,
                      granularity=None, domain="sync", features=None,
                      name=None, src_loc_at=0):