From: Megan Wachs Date: Wed, 19 Jul 2017 21:51:50 +0000 (-0700) Subject: Remove pluralization on interface names. Require clocks and resets explicitly when... X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef4f2ed888cd614858c6b2647c1eb6f988ff3973;p=sifive-blocks.git Remove pluralization on interface names. Require clocks and resets explicitly when necessary --- diff --git a/src/main/scala/devices/gpio/GPIO.scala b/src/main/scala/devices/gpio/GPIO.scala index 4884227..e7a4829 100644 --- a/src/main/scala/devices/gpio/GPIO.scala +++ b/src/main/scala/devices/gpio/GPIO.scala @@ -34,6 +34,14 @@ object IOFCtrl { // for the IOF class IOFPin extends Pin { val o = new IOFCtrl().asOutput + + def default(): Unit = { + this.o.oval := Bool(false) + this.o.oe := Bool(false) + this.o.ie := Bool(false) + this.o.valid := Bool(false) + } + def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = { this.o.oval := Bool(false) this.o.oe := Bool(false) @@ -53,7 +61,7 @@ class IOFPin extends Pin { // Connect both the i and o side of the pin, // and drive the valid signal for the IOF. -object GPIOPinToIOF { +object BasePinToIOF { def apply(pin: BasePin, iof: IOFPin): Unit = { iof <> pin iof.o.valid := Bool(true) diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala index 204f767..cd658f1 100644 --- a/src/main/scala/devices/gpio/GPIOPeriphery.scala +++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala @@ -12,7 +12,7 @@ case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] trait HasPeripheryGPIO extends HasSystemNetworks { val gpioParams = p(PeripheryGPIOKey) - val gpio = gpioParams map {params => + val gpios = gpioParams map {params => val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params)) gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) intBus.intnode := gpio.intnode @@ -28,7 +28,7 @@ trait HasPeripheryGPIOModuleImp extends LazyMultiIOModuleImp with HasPeripheryGP val outer: HasPeripheryGPIO val gpio = IO(HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))) - (gpio zip outer.gpio) foreach { case (io, device) => + (gpio zip outer.gpios) foreach { case (io, device) => io <> device.module.io.port } } diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala index b67a071..c9de71b 100644 --- a/src/main/scala/devices/i2c/I2CPeriphery.scala +++ b/src/main/scala/devices/i2c/I2CPeriphery.scala @@ -20,7 +20,7 @@ trait HasPeripheryI2C extends HasSystemNetworks { } trait HasPeripheryI2CBundle { - val i2cs: Vec[I2CPort] + val i2c: Vec[I2CPort] } trait HasPeripheryI2CModuleImp extends LazyMultiIOModuleImp with HasPeripheryI2CBundle { diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala index 73f4cfb..df6dd6f 100644 --- a/src/main/scala/devices/i2c/I2CPins.scala +++ b/src/main/scala/devices/i2c/I2CPins.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.i2c import Chisel._ +import chisel3.experimental.{withClockAndReset} import sifive.blocks.devices.pinctrl.{Pin, PinCtrl} import sifive.blocks.util.ShiftRegisterInit @@ -11,13 +12,15 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle { val scl: T = pingen() val sda: T = pingen() - def fromI2CPort(i2c: I2CPort, syncStages: Int = 0) = { - scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) - scl.o.oe := i2c.scl.oe - i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true)) + def fromI2CPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = { + withClockAndReset(clock, reset) { + scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B) + scl.o.oe := i2c.scl.oe + i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true)) - sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B) - sda.o.oe := i2c.sda.oe - i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true)) + sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B) + sda.o.oe := i2c.sda.oe + i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true)) + } } } diff --git a/src/main/scala/devices/mockaon/MockAONWrapper.scala b/src/main/scala/devices/mockaon/MockAONWrapper.scala index 6e07f80..a5fdeda 100644 --- a/src/main/scala/devices/mockaon/MockAONWrapper.scala +++ b/src/main/scala/devices/mockaon/MockAONWrapper.scala @@ -17,14 +17,14 @@ class MockAONWrapperPMUIO extends Bundle { val vddpaden = new EnhancedPin() } -class MockAONWrapperPadsIO extends Bundle { +class MockAONWrapperPins extends Bundle { val erst_n = new EnhancedPin() val lfextclk = new EnhancedPin() val pmu = new MockAONWrapperPMUIO() } class MockAONWrapperBundle extends Bundle { - val pads = new MockAONWrapperPadsIO() + val pads = new MockAONWrapperPins() val rsts = new MockAONMOffRstIO() } diff --git a/src/main/scala/devices/pinctrl/PinCtrl.scala b/src/main/scala/devices/pinctrl/PinCtrl.scala index 28beb0b..f487d39 100644 --- a/src/main/scala/devices/pinctrl/PinCtrl.scala +++ b/src/main/scala/devices/pinctrl/PinCtrl.scala @@ -21,6 +21,7 @@ abstract class Pin extends Bundle { val o: PinCtrl // Must be defined by the subclasses + def default(): Unit def inputPin(pue: Bool = Bool(false)): Bool def outputPin(signal: Bool, pue: Bool = Bool(false), @@ -28,13 +29,6 @@ abstract class Pin extends Bundle { ie: Bool = Bool(false) ): Unit - def inputPin(pins: Vec[this.type], pue: Bool): Vec[Bool] = { - val signals = Wire(Vec(pins.length, new Bool())) - for ((signal, pin) <- (signals zip pins)) { - signal := pin.inputPin(pue) - } - signals - } } @@ -43,6 +37,12 @@ abstract class Pin extends Bundle { class BasePin extends Pin() { val o = new PinCtrl().asOutput + def default(): Unit = { + this.o.oval := Bool(false) + this.o.oe := Bool(false) + this.o.ie := Bool(false) + } + def inputPin(pue: Bool = Bool(false) /*ignored*/): Bool = { this.o.oval := Bool(false) this.o.oe := Bool(false) @@ -59,7 +59,6 @@ class BasePin extends Pin() { this.o.oe := Bool(true) this.o.ie := ie } - } ///////////////////////////////////////////////////////////////////////// @@ -72,6 +71,14 @@ class EnhancedPin extends Pin() { val o = new EnhancedPinCtrl().asOutput + def default(): Unit = { + this.o.oval := Bool(false) + this.o.oe := Bool(false) + this.o.ie := Bool(false) + this.o.ds := Bool(false) + this.o.pue := Bool(false) + } + def inputPin(pue: Bool = Bool(false)): Bool = { this.o.oval := Bool(false) this.o.oe := Bool(false) diff --git a/src/main/scala/devices/pwm/PWMPeriphery.scala b/src/main/scala/devices/pwm/PWMPeriphery.scala index 63bbfab..31ad5f6 100644 --- a/src/main/scala/devices/pwm/PWMPeriphery.scala +++ b/src/main/scala/devices/pwm/PWMPeriphery.scala @@ -38,15 +38,15 @@ trait HasPeripheryPWM extends HasSystemNetworks { } trait HasPeripheryPWMBundle { - val pwms: HeterogeneousBag[PWMPortIO] + val pwm: HeterogeneousBag[PWMPortIO] } trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp with HasPeripheryPWMBundle { val outer: HasPeripheryPWM - val pwms = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))) + val pwm = IO(HeterogeneousBag(outer.pwmParams.map(new PWMPortIO(_)))) - (pwms zip outer.pwms) foreach { case (io, device) => + (pwm zip outer.pwms) foreach { case (io, device) => io.port := device.module.io.gpio } } diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index f95be7e..f2b3b41 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -21,15 +21,15 @@ trait HasPeripherySPI extends HasSystemNetworks { } trait HasPeripherySPIBundle { - val spis: HeterogeneousBag[SPIPortIO] + val spi: HeterogeneousBag[SPIPortIO] } trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle { val outer: HasPeripherySPI - val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))) + val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_)))) - (spis zip outer.spis).foreach { case (io, device) => + (spi zip outer.spis).foreach { case (io, device) => io <> device.module.io.port } } @@ -38,7 +38,7 @@ case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]] trait HasPeripherySPIFlash extends HasSystemNetworks { val spiFlashParams = p(PeripherySPIFlashKey) - val qspi = spiFlashParams map { params => + val qspis = spiFlashParams map { params => val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params)) qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node)) @@ -56,7 +56,7 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe val outer: HasPeripherySPIFlash val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_)))) - (qspi zip outer.qspi) foreach { case (io, device) => + (qspi zip outer.qspis) foreach { case (io, device) => io <> device.module.io.port } } diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala index c501316..346f8ee 100644 --- a/src/main/scala/devices/spi/SPIPins.scala +++ b/src/main/scala/devices/spi/SPIPins.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.spi import Chisel._ +import chisel3.experimental.{withClockAndReset} import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) { @@ -10,19 +11,22 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) val dq: Vec[T] = Vec(4, pingen()) val cs: Vec[T] = Vec(c.csWidth, pingen()) - def fromSPIPort(spi: SPIPortIO, syncStages: Int = 0, driveStrength: Bool = Bool(false)) { - - sck.outputPin(spi.sck, ds = driveStrength) + def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool, + syncStages: Int = 0, driveStrength: Bool = Bool(false)) { - (dq zip spi.dq).foreach {case (p, s) => - p.outputPin(s.o, pue = Bool(true), ds = driveStrength) - p.o.oe := s.oe - p.o.ie := ~s.oe - s.i := ShiftRegister(p.i.ival, syncStages) - } + withClockAndReset(clock, reset) { + sck.outputPin(spi.sck, ds = driveStrength) + + (dq zip spi.dq).foreach {case (p, s) => + p.outputPin(s.o, pue = Bool(true), ds = driveStrength) + p.o.oe := s.oe + p.o.ie := ~s.oe + s.i := ShiftRegister(p.i.ival, syncStages) + } - (cs zip spi.cs) foreach { case (c, s) => - c.outputPin(s, ds = driveStrength) + (cs zip spi.cs) foreach { case (c, s) => + c.outputPin(s, ds = driveStrength) + } } } } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index 58c61f5..d94d518 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -2,6 +2,7 @@ package sifive.blocks.devices.uart import Chisel._ +import chisel3.experimental.{withClockAndReset} import freechips.rocketchip.config.Field import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.chip.HasSystemNetworks @@ -22,31 +23,33 @@ trait HasPeripheryUART extends HasSystemNetworks { } trait HasPeripheryUARTBundle { - val uarts: Vec[UARTPortIO] + val uart: Vec[UARTPortIO] def tieoffUARTs(dummy: Int = 1) { - uarts.foreach { _.rxd := UInt(1) } + uart.foreach { _.rxd := UInt(1) } } } trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle { val outer: HasPeripheryUART - val uarts = IO(Vec(outer.uartParams.size, new UARTPortIO)) + val uart = IO(Vec(outer.uartParams.size, new UARTPortIO)) - (uarts zip outer.uarts).foreach { case (io, device) => + (uart zip outer.uarts).foreach { case (io, device) => io <> device.module.io.port } } -class UARTPins(pingen: () => Pin) extends Bundle { +class UARTPins[T <: Pin] (pingen: () => T) extends Bundle { val rxd = pingen() val txd = pingen() - def fromUARTPort(uart: UARTPortIO, syncStages: Int = 0) { - txd.outputPin(uart.txd) - val rxd_t = rxd.inputPin() - uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true)) + def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) { + withClockAndReset(clock, reset) { + txd.outputPin(uart.txd) + val rxd_t = rxd.inputPin() + uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true)) + } } }