From: Raptor Engineering Development Team <support@raptorengineering.com>
Date: Thu, 7 Apr 2022 18:39:38 +0000 (-0500)
Subject: Working at 50MHz system clock
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0d033795543fd6c451c709713347aa5ce983202;p=gram.git

Working at 50MHz system clock
---

diff --git a/examples/headless-versa-85.py b/examples/headless-versa-85.py
index d2692e5..3050f89 100644
--- a/examples/headless-versa-85.py
+++ b/examples/headless-versa-85.py
@@ -31,23 +31,32 @@ class DDR3SoC(SoC, Elaboratable):
         self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
                                          features={"cti", "bte"})
 
+        #desired_sys_clk_freq = 100e6
+        #desired_sys_clk_freq = 90e6
+        #desired_sys_clk_freq = 75e6
+        #desired_sys_clk_freq = 70e6
+        #desired_sys_clk_freq = 65e6
+        #desired_sys_clk_freq = 60e6
+        #desired_sys_clk_freq = 55e6
+        desired_sys_clk_freq = 50e6
+
         #self.crg = ECPIX5CRG()
-        self.crg = ECP5CRG()
+        self.crg = ECP5CRG(sys_clk_freq=desired_sys_clk_freq)
 
-        self.ub = UARTBridge(divisor=868, pins=platform.request("uart", 0))
+        self.ub = UARTBridge(divisor=int(desired_sys_clk_freq/115200), pins=platform.request("uart", 0))
 
         ddr_pins = platform.request("ddr3", 0, dir={"dq":"-", "dqs":"-"},
             xdr={"clk":4, "a":4, "ba":4, "clk_en":4, "odt":4, "ras":4, "cas":4, "we":4, "cs":4, "rst":1})
         self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
         self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
 
-        ddrmodule = MT41K64M16(platform.default_clk_frequency, "1:2")
+        ddrmodule = MT41K64M16(self.crg.sys_clk_freq, "1:2")
 
         self.dramcore = DomainRenamer("dramsync")(gramCore(
             phy=self.ddrphy,
             geom_settings=ddrmodule.geom_settings,
             timing_settings=ddrmodule.timing_settings,
-            clk_freq=platform.default_clk_frequency))
+            clk_freq=self.crg.sys_clk_freq))
         self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
 
         self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
@@ -55,7 +64,7 @@ class DDR3SoC(SoC, Elaboratable):
 
         self.memory_map = self._decoder.bus.memory_map
 
-        self.clk_freq = platform.default_clk_frequency
+        self.clk_freq = self.crg.sys_clk_freq
 
     def elaborate(self, platform):
         m = Module()
diff --git a/examples/headless/main.c b/examples/headless/main.c
index 35e6b46..37d22bd 100644
--- a/examples/headless/main.c
+++ b/examples/headless/main.c
@@ -122,13 +122,22 @@ int main(int argc, char *argv[]) {
 #if 0
 	struct gramProfile profile = {
 		.mode_registers = {
-			0xb20, 0x806, 0x200, 0x0
+			0xb30, 0x806, 0x200, 0x0
 		},
 		.rdly_p0 = 2,
 		.rdly_p1 = 2,
 	};
 #endif
 #if 1
+	struct gramProfile profile = {
+		.mode_registers = {
+			0xb20, 0x806, 0x200, 0x0
+		},
+		.rdly_p0 = 2,
+		.rdly_p1 = 2,
+	};
+#endif
+#if 0
 	struct gramProfile profile = {
 		.mode_registers = {
 			0x320, 0x6, 0x200, 0x0