From: Luke Kenneth Casson Leighton Date: Wed, 19 Jan 2022 12:36:02 +0000 (+0000) Subject: add (commented-out) SVSRR0 DMI dump X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0f12571c13392ea33064649036c57c5a2e37b03;p=libresoc-litex.git add (commented-out) SVSRR0 DMI dump --- diff --git a/sim.py b/sim.py index 3a74235..47c7684 100755 --- a/sim.py +++ b/sim.py @@ -11,6 +11,7 @@ import os import argparse from migen import (Signal, FSM, If, Display, Finish, NextValue, NextState) +from migen import Display as D from litex.build.generic_platform import Pins, Subsignal from litex.build.sim import SimPlatform @@ -64,8 +65,8 @@ class LibreSoCSim(SoCSDRAM): "tests/decrementer/decrementer.bin" #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ # "hello_world/hello_world.bin" - #ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ - # "tests/mmu/mmu.bin" + ram_fname = "/home/lkcl/src/libresoc/microwatt/" \ + "tests/mmu/mmu.bin" #ram_fname = None # reserve XICS ICP and XICS memory addresses. @@ -332,6 +333,7 @@ class LibreSoCSim(SoCSDRAM): If(regnum == 43, Display(" HSPRG1: %016x", dbg_dout),), # HSPRG1 If(regnum == 44, Display(" XER: %016x", dbg_dout),), # XER If(regnum == 45, Display(" TAR: %016x", dbg_dout),), # TAR + #If(regnum == 46, Display(" SVSRR0: %016x", dbg_dout),), # SVSRR0 ), # also check if this is a "stat" If(dbg_addr == 1, # requested a STAT