From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 14 Apr 2022 11:51:02 +0000 (+0100)
Subject: add verilog-wishbone (for async bridge) to hdl-dev-ls2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f88d6a87dbb070ce92b38b9061766f2b3fc29b84;p=dev-env-setup.git

add verilog-wishbone (for async bridge) to hdl-dev-ls2
---

diff --git a/hdl-dev-ls2 b/hdl-dev-ls2
index 34a801a..3e58228 100755
--- a/hdl-dev-ls2
+++ b/hdl-dev-ls2
@@ -14,6 +14,7 @@ git clone https://git.libre-soc.org/git/lambdasoc.git
 git clone https://git.libre-soc.org/git/microwatt.git tercel-qspi
 git clone https://github.com/freecores/uart16550
 git clone https://github.com/freecores/ethmac
+git clone https://github.com/alexforencich/verilog-wishbone
 
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 # lambdasoc