From: Jacob Lifshay Date: Wed, 22 Dec 2021 01:02:34 +0000 (-0800) Subject: remove unnecessary messages X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fabba809f4c1e423729002026faaea1ae81630fc;p=nmutil.git remove unnecessary messages --- diff --git a/src/nmutil/grev.py b/src/nmutil/grev.py index c529bbc..166414c 100644 --- a/src/nmutil/grev.py +++ b/src/nmutil/grev.py @@ -37,7 +37,7 @@ def grev(inval, chunk_sizes, log2_width): class GRev(Elaboratable): - """ <--no space here>Generalized bit-reverse. + """Generalized bit-reverse. https://bugs.libre-soc.org/show_bug.cgi?id=755 diff --git a/src/nmutil/lut.py b/src/nmutil/lut.py index 4b254fc..261a1d1 100644 --- a/src/nmutil/lut.py +++ b/src/nmutil/lut.py @@ -17,7 +17,7 @@ from nmigen.cli import rtlil class BitwiseMux(Elaboratable): - """ <- XXX no space here>Mux, but treating input/output Signals as bit vectors, rather than + """Mux, but treating input/output Signals as bit vectors, rather than integers. This means each bit in the output is independently multiplexed based on the corresponding bit in each of the inputs. """ @@ -35,10 +35,10 @@ class BitwiseMux(Elaboratable): class BitwiseLut(Elaboratable): - """ <- XXX no space here>Bitwise logic operators implemented using a look-up table, like LUTs in - FPGAs. Inspired by x86's `vpternlog[dq]` instructions. + """Bitwise logic operators implemented using a look-up table, like LUTs in + FPGAs. Inspired by x86's `vpternlog[dq]` instructions. - Each output bit `i` is set to `lut[Cat(inp[i] for inp in self.inputs)]` + Each output bit `i` is set to `lut[Cat(inp[i] for inp in self.inputs)]` """ def __init__(self, input_count, width): @@ -81,10 +81,10 @@ class BitwiseLut(Elaboratable): class TreeBitwiseLut(Elaboratable): - """ <- XXX no space here>Tree-based version of BitwiseLut. See BitwiseLut for API documentation. - (good enough reason to say "see bitwiselut", but mention that - the API is identical and explain why the second implementation - exists, despite it being identical) + """Tree-based version of BitwiseLut. See BitwiseLut for API documentation. + (good enough reason to say "see bitwiselut", but mention that + the API is identical and explain why the second implementation + exists, despite it being identical) """ def __init__(self, input_count, width):