From: Luke Kenneth Casson Leighton Date: Fri, 18 Feb 2022 19:42:44 +0000 (+0000) Subject: reduce number of d-cache lines in microwatt fpga mode X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=fdd55337edc5856dc5ae0c35cd6ad28151bfc441;p=soc.git reduce number of d-cache lines in microwatt fpga mode --- diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py index 04c222fa..3b67b7cf 100644 --- a/src/soc/experiment/dcache.py +++ b/src/soc/experiment/dcache.py @@ -745,7 +745,7 @@ class DCache(Elaboratable, DCacheConfig): if self.microwatt_compat: # reduce way sizes and num lines - super().__init__(NUM_LINES = 16, + super().__init__(NUM_LINES = 8, NUM_WAYS = 1, TLB_NUM_WAYS = 1, TLB_SET_SIZE=16) # XXX needs device-tree entry