begin working on linux verilator simulation
[microwatt.git] / Makefile
2022-04-13 Tobias Platenbegin working on linux verilator simulation tplaten_3d_game
2022-04-12 Tobias Platencleanup Makefile
2022-03-31 Tobias Platenbuilding microwatt-verilator with external core now...
2022-03-30 Tobias Platenadd external core option
2022-03-30 Tobias Platenbegin merge of soc.vhdl, fix Makefile
2022-03-28 Tobias Platenadd read_verilog when using external core
2022-03-27 Tobias Platenmore work on verilator backport
2022-03-27 Tobias Platenbegin verilator_trace backport
2022-03-24 Tobias Platentry using plru_dummy.vhdl
2022-03-23 Tobias Platenpartial synthesize with EXTERNAL_CORE
2022-03-23 Tobias Platenallow using external core
2022-03-22 Tobias PlatenMerge remote-tracking branch 'to-be-merged/merge-3d... merge-3d-game
2022-03-04 Matt JohnstonMakefile: Don't force generic USE_LITEDRAM=true
2022-03-04 Matt Johnstonvalentyusb: Add USB UART to SOC and OrangeCrab
2022-03-04 Matt JohnstonMakefile: depend on soc_extra_v
2022-02-23 Michael NeulingMerge pull request #348 from paulusmack/reduce
2022-02-07 Michael NeulingMerge pull request #346 from mkj/dmi_ecp5
2022-02-07 Anton BlanchardMerge pull request #343 from mikey/orange-crab-ci
2022-02-04 Matt Johnstondmi_dtm_ecp5: Use ECP5 JTAGG for DMI
2022-02-04 Paul MackerrasMerge pull request #345 from antonblanchard/popcnt...
2022-02-02 Paul Mackerrascore: Make popcnt* take two cycles
2022-01-18 Michael NeulingMerge pull request #342 from mkj/orangecrab-merge
2022-01-18 Michael NeulingMerge branch 'master' into orangecrab-merge
2022-01-18 Michael NeulingMerge pull request #341 from mkj/progtools
2022-01-18 Michael NeulingMerge pull request #340 from mkj/orangecrab-ghdl-plugin
2022-01-17 Matt Johnstonorangecrab: use litesdcard
2022-01-17 Matt Johnstonorangecrab: add Orange Crab r0.2 target
2022-01-13 Matt JohnstonMakefile: add ecpprog targets
2022-01-13 Matt JohnstonMakefile: Add DFU programming
2022-01-13 Matt JohnstonMakefile: detect when ghdl is a yosys plugin
2022-01-08 Anton BlanchardMerge pull request #338 from shenki/yosys-read-verilog
2021-12-21 Joel StanleyMakefile: Use read_verilog with yosys
2021-10-13 Michael NeulingMerge pull request #336 from paulusmack/fixes
2021-10-12 Paul MackerrasMakefile: Add a target for the Orange Crab v0.21 with...
2021-09-24 Paul MackerrasMerge pull request #330 from antonblanchard/orange...
2021-09-24 Anton BlanchardOrange Crab is 48MHz not 50MHz, bump PLL frequency
2021-09-03 Michael NeulingMerge pull request #322 from paulusmack/fixes
2021-08-17 Michael NeulingMerge pull request #319 from antonblanchard/verilator-ci
2021-08-14 Anton Blanchardmakefile: Check environment for MEMORY_SIZE/RAM_INIT_FILE
2021-08-14 Anton Blanchardmakefile: Add some verilator micropython tests
2021-08-14 Anton Blanchardverilator: Specify top level module
2021-08-14 Anton Blanchardmakefile: Simplify microwatt-verilator target, add...
2021-08-11 Michael NeulingMerge pull request #315 from paulusmack/pmu
2021-08-11 Paul MackerrasMerge pull request #314 from antonblanchard/yosys-go...
2021-08-11 Paul Mackerrascore: Add a basic performance monitor unit (PMU) implem...
2021-08-11 Anton BlanchardReduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut
2021-08-04 Anton BlanchardMerge pull request #299 from mikey/vunit-make
2021-08-02 Michael Neulingmakefile: Add check_vunit
2021-07-31 Michael NeulingReduce the size of icache to help yosys ECP5 builds...
2021-06-21 Michael NeulingMerge pull request #298 from paulusmack/master
2021-06-21 Michael NeulingMerge pull request #295 from LarsAsplund/master
2021-06-09 Lars AsplundMake core testbenches recognized by VUnit
2021-05-17 Michael NeulingMerge pull request #277 from paulus/gpio
2021-05-11 Paul MackerrasMerge pull request #278 from shenki/openocd-v0.11
2021-05-05 Paul MackerrasMerge pull request #283 from antonblanchard/whitespace
2021-03-25 Anton BlanchardMerge pull request #286 from antonblanchard/Makefile...
2021-03-25 Anton BlanchardRemove unused GHDL_TARGET_GENERICS
2021-03-25 Anton BlanchardMove verilator --trace flag into VERILATOR_FLAGS
2021-03-24 Anton BlanchardMerge pull request #285 from antonblanchard/Makefile...
2021-03-24 Anton BlanchardRemove -frelaxed
2021-03-24 Anton BlanchardUse VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator...
2021-03-24 Anton BlanchardRemove core_files from soc_files and fpga_files
2021-02-24 Paul MackerrasAdd a GPIO controller and use it to drive the shield...
2021-02-08 Michael NeulingMerge pull request #269 from paulusmack/pipeline
2021-01-18 Paul Mackerrascore: Track CR hazards and bypasses using tags
2021-01-18 Paul Mackerrascore: Track GPR hazards using tags that propagate throu...
2020-12-08 Anton BlanchardMerge pull request #255 from antonblanchard/log-length
2020-12-08 Anton BlanchardMerge pull request #254 from antonblanchard/fix-verilator
2020-12-07 Anton BlanchardAdd verilator FPGA target
2020-12-07 Anton BlanchardMerge pull request #253 from antonblanchard/fix-verilator
2020-12-07 Anton BlanchardFix verilator build
2020-12-01 Michael NeulingMerge pull request #249 from paulusmack/master
2020-12-01 Michael NeulingMerge pull request #250 from umarcor/containers
2020-11-30 umarcormakefile: update synthesis containers
2020-11-30 umarcormakefile: whitespace cleanup
2020-09-17 Michael NeulingMerge pull request #245 from paulusmack/fpu
2020-09-03 Paul Mackerrascore: Add framework for an FPU
2020-08-13 Michael NeulingMerge pull request #235 from paulusmack/master
2020-08-06 Paul MackerrasAdd random number generator and implement the darn...
2020-07-09 Michael NeulingMerge pull request #222 from iamjpn/master
2020-07-08 Paul MackerrasMerge pull request #223 from mikey/ecp5
2020-07-07 Michael NeulingAdd PLL for ECP5 device
2020-07-07 Anton BlanchardMerge pull request #220 from mikey/ghdl-makefile
2020-07-07 Anton BlanchardMerge pull request #209 from mikey/yosys
2020-07-04 Michael NeulingUse $(GHDL) rather than ghdl in Makefile
2020-07-02 Michael NeulingAdd FPGA_TARGET=ECP5-EVN make option for synthesis...
2020-07-02 Michael NeulingAdd SYNTH_ECP5_FLAGS option for building
2020-07-02 Michael NeulingAdd ram file to synthesis build dependencies
2020-07-02 Michael NeulingAdd uart16550 files to yosys/nextpnr build
2020-07-02 Michael NeulingBuild to tmp file so nextpnr errors don't confuse make
2020-07-02 Michael NeulingFix building with yosys/nextpnr
2020-06-30 Paul MackerrasMerge pull request #206 from Jbalkind/icachecleanup
2020-06-29 Michael NeulingMerge pull request #213 from ozbenh/uart16550
2020-06-23 Benjamin Herrenschmidtuart: Add a simulation model for the 16550 compatible...
2020-06-23 Benjamin Herrenschmidtuart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
2020-06-19 Michael NeulingMerge pull request #208 from paulusmack/faster
2020-06-13 Paul Mackerrascore: Remove fetch2 pipeline stage
2020-06-13 Paul MackerrasMerge pull request #204 from ozbenh/spi
2020-06-13 Benjamin Herrenschmidtspi: Add simulation support
2020-06-09 Michael NeulingMerge pull request #196 from ozbenh/makefile-lib-fix
next