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begin working on linux verilator simulation
[microwatt.git]
/
Makefile
2022-04-13
Tobias Platen
begin working on linux verilator simulation
tplaten_3d_game
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2022-04-12
Tobias Platen
cleanup Makefile
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2022-03-31
Tobias Platen
building microwatt-verilator with external core now...
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2022-03-30
Tobias Platen
add external core option
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2022-03-30
Tobias Platen
begin merge of soc.vhdl, fix Makefile
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2022-03-28
Tobias Platen
add read_verilog when using external core
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2022-03-27
Tobias Platen
more work on verilator backport
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2022-03-27
Tobias Platen
begin verilator_trace backport
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2022-03-24
Tobias Platen
try using plru_dummy.vhdl
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2022-03-23
Tobias Platen
partial synthesize with EXTERNAL_CORE
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2022-03-23
Tobias Platen
allow using external core
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2022-03-22
Tobias Platen
Merge remote-tracking branch 'to-be-merged/merge-3d...
merge-3d-game
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2022-03-04
Matt Johnston
Makefile: Don't force generic USE_LITEDRAM=true
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2022-03-04
Matt Johnston
valentyusb: Add USB UART to SOC and OrangeCrab
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2022-03-04
Matt Johnston
Makefile: depend on soc_extra_v
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2022-02-23
Michael Neuling
Merge pull request #348 from paulusmack/reduce
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2022-02-07
Michael Neuling
Merge pull request #346 from mkj/dmi_ecp5
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2022-02-07
Anton Blanchard
Merge pull request #343 from mikey/orange-crab-ci
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2022-02-04
Matt Johnston
dmi_dtm_ecp5: Use ECP5 JTAGG for DMI
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2022-02-04
Paul Mackerras
Merge pull request #345 from antonblanchard/popcnt...
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2022-02-02
Paul Mackerras
core: Make popcnt* take two cycles
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2022-01-18
Michael Neuling
Merge pull request #342 from mkj/orangecrab-merge
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2022-01-18
Michael Neuling
Merge branch 'master' into orangecrab-merge
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2022-01-18
Michael Neuling
Merge pull request #341 from mkj/progtools
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2022-01-18
Michael Neuling
Merge pull request #340 from mkj/orangecrab-ghdl-plugin
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2022-01-17
Matt Johnston
orangecrab: use litesdcard
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2022-01-17
Matt Johnston
orangecrab: add Orange Crab r0.2 target
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2022-01-13
Matt Johnston
Makefile: add ecpprog targets
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2022-01-13
Matt Johnston
Makefile: Add DFU programming
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2022-01-13
Matt Johnston
Makefile: detect when ghdl is a yosys plugin
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2022-01-08
Anton Blanchard
Merge pull request #338 from shenki/yosys-read-verilog
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2021-12-21
Joel Stanley
Makefile: Use read_verilog with yosys
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2021-10-13
Michael Neuling
Merge pull request #336 from paulusmack/fixes
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2021-10-12
Paul Mackerras
Makefile: Add a target for the Orange Crab v0.21 with...
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2021-09-24
Paul Mackerras
Merge pull request #330 from antonblanchard/orange...
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2021-09-24
Anton Blanchard
Orange Crab is 48MHz not 50MHz, bump PLL frequency
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2021-09-03
Michael Neuling
Merge pull request #322 from paulusmack/fixes
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2021-08-17
Michael Neuling
Merge pull request #319 from antonblanchard/verilator-ci
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2021-08-14
Anton Blanchard
makefile: Check environment for MEMORY_SIZE/RAM_INIT_FILE
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2021-08-14
Anton Blanchard
makefile: Add some verilator micropython tests
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2021-08-14
Anton Blanchard
verilator: Specify top level module
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2021-08-14
Anton Blanchard
makefile: Simplify microwatt-verilator target, add...
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2021-08-11
Michael Neuling
Merge pull request #315 from paulusmack/pmu
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2021-08-11
Paul Mackerras
Merge pull request #314 from antonblanchard/yosys-go...
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2021-08-11
Paul Mackerras
core: Add a basic performance monitor unit (PMU) implem...
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2021-08-11
Anton Blanchard
Reduce Yosys ECP5 cell usage by 30% with -abc9 -nowidelut
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2021-08-04
Anton Blanchard
Merge pull request #299 from mikey/vunit-make
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2021-08-02
Michael Neuling
makefile: Add check_vunit
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2021-07-31
Michael Neuling
Reduce the size of icache to help yosys ECP5 builds...
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2021-06-21
Michael Neuling
Merge pull request #298 from paulusmack/master
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2021-06-21
Michael Neuling
Merge pull request #295 from LarsAsplund/master
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2021-06-09
Lars Asplund
Make core testbenches recognized by VUnit
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2021-05-17
Michael Neuling
Merge pull request #277 from paulus/gpio
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2021-05-11
Paul Mackerras
Merge pull request #278 from shenki/openocd-v0.11
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2021-05-05
Paul Mackerras
Merge pull request #283 from antonblanchard/whitespace
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2021-03-25
Anton Blanchard
Merge pull request #286 from antonblanchard/Makefile...
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2021-03-25
Anton Blanchard
Remove unused GHDL_TARGET_GENERICS
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2021-03-25
Anton Blanchard
Move verilator --trace flag into VERILATOR_FLAGS
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2021-03-24
Anton Blanchard
Merge pull request #285 from antonblanchard/Makefile...
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2021-03-24
Anton Blanchard
Remove -frelaxed
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2021-03-24
Anton Blanchard
Use VERILATOR_FLAGS/VERILATOR_CFLAGS on all verilator...
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2021-03-24
Anton Blanchard
Remove core_files from soc_files and fpga_files
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2021-02-24
Paul Mackerras
Add a GPIO controller and use it to drive the shield...
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2021-02-08
Michael Neuling
Merge pull request #269 from paulusmack/pipeline
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2021-01-18
Paul Mackerras
core: Track CR hazards and bypasses using tags
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2021-01-18
Paul Mackerras
core: Track GPR hazards using tags that propagate throu...
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2020-12-08
Anton Blanchard
Merge pull request #255 from antonblanchard/log-length
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2020-12-08
Anton Blanchard
Merge pull request #254 from antonblanchard/fix-verilator
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2020-12-07
Anton Blanchard
Add verilator FPGA target
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2020-12-07
Anton Blanchard
Merge pull request #253 from antonblanchard/fix-verilator
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2020-12-07
Anton Blanchard
Fix verilator build
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2020-12-01
Michael Neuling
Merge pull request #249 from paulusmack/master
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2020-12-01
Michael Neuling
Merge pull request #250 from umarcor/containers
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2020-11-30
umarcor
makefile: update synthesis containers
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2020-11-30
umarcor
makefile: whitespace cleanup
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2020-09-17
Michael Neuling
Merge pull request #245 from paulusmack/fpu
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2020-09-03
Paul Mackerras
core: Add framework for an FPU
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2020-08-13
Michael Neuling
Merge pull request #235 from paulusmack/master
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2020-08-06
Paul Mackerras
Add random number generator and implement the darn...
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2020-07-09
Michael Neuling
Merge pull request #222 from iamjpn/master
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2020-07-08
Paul Mackerras
Merge pull request #223 from mikey/ecp5
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2020-07-07
Michael Neuling
Add PLL for ECP5 device
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2020-07-07
Anton Blanchard
Merge pull request #220 from mikey/ghdl-makefile
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2020-07-07
Anton Blanchard
Merge pull request #209 from mikey/yosys
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2020-07-04
Michael Neuling
Use $(GHDL) rather than ghdl in Makefile
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2020-07-02
Michael Neuling
Add FPGA_TARGET=ECP5-EVN make option for synthesis...
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2020-07-02
Michael Neuling
Add SYNTH_ECP5_FLAGS option for building
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2020-07-02
Michael Neuling
Add ram file to synthesis build dependencies
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2020-07-02
Michael Neuling
Add uart16550 files to yosys/nextpnr build
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2020-07-02
Michael Neuling
Build to tmp file so nextpnr errors don't confuse make
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2020-07-02
Michael Neuling
Fix building with yosys/nextpnr
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2020-06-30
Paul Mackerras
Merge pull request #206 from Jbalkind/icachecleanup
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2020-06-29
Michael Neuling
Merge pull request #213 from ozbenh/uart16550
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2020-06-23
Benjamin Herrenschmidt
uart: Add a simulation model for the 16550 compatible...
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2020-06-23
Benjamin Herrenschmidt
uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl
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2020-06-19
Michael Neuling
Merge pull request #208 from paulusmack/faster
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2020-06-13
Paul Mackerras
core: Remove fetch2 pipeline stage
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2020-06-13
Paul Mackerras
Merge pull request #204 from ozbenh/spi
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2020-06-13
Benjamin Herrenschmidt
spi: Add simulation support
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2020-06-09
Michael Neuling
Merge pull request #196 from ozbenh/makefile-lib-fix
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