add hierarchy -smtcheck
[yosys.git] / backends /
2022-06-07 Jacob Lifshaysmt2: Add smtlib2_comb_expr attribute to allow user...
2022-06-07 Jannis Hardersmtbmc: recognize cvc5 and fix unrolling for cvc4/cvc5
2022-06-07 Jacob Lifshayadd $divfloor support to write_smt2
2022-05-26 Aki Van Nesspass jny: flipped the defaults for the inclusion of... yosys-0.13-with-write_jny
2022-05-26 Aki Van Nesspass jny: ensured the cell collection is cleared betwee...
2022-05-26 Aki Van Nesspass jny: fixed missing quotes around the type value...
2022-05-26 Aki Van Nesspass jny: fixed the backslash escape for strings
2022-05-26 Aki Van Nesspass jny: removed the invalid json escapes
2022-05-26 Aki Van Nesspass jny: added some todo comments about things that...
2022-05-26 Aki Van Nesspass jny: changed the constructor initializers to use...
2022-05-26 Aki Van Nesspass jny: fixed the string escape method to be less...
2022-05-26 Aki Van Nesspass jny: fixed the signed output for param value output
2022-05-26 Aki Van Nesspass jny: added connection output
2022-05-26 Aki Van Nesspass jny: added filter options for including connection...
2022-05-26 Aki Van Nesspass jny: large chunk of refactoring to make the JSON...
2022-05-26 Aki Van Nessmetadata -> jny: migrated to the proper name for the...
2022-05-26 Aki Van Nesspass metadata: added the machinery to write param and...
2022-05-26 Aki Van Nesspass metadata: removed superfluous `stringf` calls
2022-05-26 Aki Van Nesspass metadata: some more rough work on dumping the...
2022-05-26 Aki Van Nesspass metadata: fixed the MetadataWriter object initiali...
2022-05-26 Aki Van Nesspass metadata: added the output of parameters,
2022-05-26 Aki Van Nesspass metadata: fixed some of the output formatting
2022-05-26 Aki Van Nesspass metadata: initial commit of the metadata pass...
2021-12-25 CatherineMerge pull request #3127 from whitequark/cxxrtl-no...
2021-12-25 Catherinecxxrtl: don't reset elided wires with \init attribute.
2021-12-16 CatherineMerge pull request #3115 from whitequark/issue-3112
2021-12-15 Catherinecxxrtl: demote wires not inlinable only in debug_eval...
2021-12-12 Marcelina KościelnickaAdd clean_zerowidth pass, use it for Verilog output.
2021-12-12 CatherineMerge pull request #3105 from whitequark/cxxrtl-reset...
2021-12-12 Marcelina Kościelnickartlil: Dump empty connections when whole module is...
2021-12-11 Catherinecxxrtl: preserve interior memory pointers across reset.
2021-12-11 CatherineMerge pull request #3103 from whitequark/write_verilog...
2021-12-11 whitequarkcxxrtl: use unique_ptr<value<>[]> to store memory contents.
2021-12-11 whitequarkwrite_verilog: dump zero width sigspecs correctly.
2021-11-25 Loftysta: very crude static timing analysis pass
2021-11-17 Miodrag MilanovićMerge pull request #3080 from YosysHQ/micko/init_wire
2021-11-17 Miodrag MilanovicGive initial wire unique ID, fixes #2914
2021-10-11 Claire XenMerge pull request #3039 from YosysHQ/claire/verific_aldff
2021-10-11 Claire XenMerge pull request #3040 from YosysHQ/micko/split_modul...
2021-10-09 Miodrag MilanovicSplit module ports, 20 per line
2021-10-02 Marcelina KościelnickaHook up $aldff support in various passes.
2021-10-02 Marcelina Kościelnickakernel/ff: Refactor FfData to enable FFs with async...
2021-09-28 Miodrag MilanovićMerge pull request #3017 from YosysHQ/claire/short_rtli...
2021-09-27 Claire Xenia WolfAdd optimization to rtlil back-end for all-x parameter...
2021-09-18 Miodrag MilanovićMerge pull request #3010 from the6p4c/master
2021-09-17 the6p4cFix protobuf backend build dependencies
2021-09-10 Marcelina Kościelnickayosys-smtbmc: Fix reused loop variable.
2021-08-10 Marcelina Kościelnickakernel/mem: Introduce transparency masks.
2021-08-01 Marcelina Kościelnickabackend/verilog: Add alternate mode for transparent...
2021-07-28 Marcelina Kościelnickabackends/verilog: Support meminit with mask.
2021-07-20 whitequarkMerge pull request #2885 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkMerge pull request #2884 from whitequark/cxxrtl-fix...
2021-07-20 whitequarkcxxrtl: treat wires with multiple defs as not inlinable.
2021-07-20 whitequarkcxxrtl: treat assignable internal wires used only for...
2021-07-20 whitequarkMerge pull request #2881 from whitequark/cxxrtl-sideway...
2021-07-19 whitequarkcxxrtl: escape colon in variable names in VCD writer.
2021-07-18 whitequarkMerge pull request #2880 from whitequark/cxxrtl-fix...
2021-07-18 whitequarkcxxrtl: add debug_item::{get,set}.
2021-07-17 whitequarkMerge pull request #2879 from whitequark/cxxrtl-fix...
2021-07-17 whitequarkcxxrtl: treat internal wires used only for debug as...
2021-07-16 whitequarkMerge pull request #2874 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkMerge pull request #2873 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkMerge pull request #2872 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkcxxrtl: run hierarchy pass regardless of (*top*) attrib...
2021-07-16 whitequarkcxxrtl: emit debug items for unused public wires.
2021-07-16 whitequarkcxxrtl: don't expect user cell inputs to be wires.
2021-07-16 whitequarkMerge pull request #2871 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkcxxrtl: don't mark buffered internal wires as UNUSED...
2021-07-16 whitequarkMerge pull request #2870 from whitequark/cxxrtl-fix...
2021-07-15 whitequarkcxxrtl: mark dead local wires as unused even with inlin...
2021-07-13 Marcelina Kościelnickakernel/mem: Add a coalesce_inits helper.
2021-07-12 GCHQDeveloper560Add support for the Bitwuzla solver
2021-07-12 Marcelina Kościelnickacxxrtl: Support memory writes in processes.
2021-07-12 Marcelina Kościelnickacxxrtl: Add support for memory read port reset.
2021-07-12 Marcelina Kościelnickacxxrtl: Add support for mem read port initial data.
2021-07-12 Marcelina Kościelnickacxxrtl: Convert to Mem helpers.
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-09 Claire Xenia WolfIntersynth URL
2021-06-07 Claire Xenia WolfFixing old e-mail addresses and deadnames
2021-05-27 Marcelina KościelnickaMake a few passes auto-call Mem::narrow instead of...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add support for memory read port...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add wide port support.
2021-05-25 Marcelina Kościelnickabackends/verilog: Try to preserve mem write port priori...
2021-05-25 Marcelina KościelnickaReject wide ports in some passes that will never suppor...
2021-05-24 Marcelina Kościelnickabackend/firrtl: Convert to use Mem helpers.
2021-05-23 Marcelina Kościelnickabtor: Use is_mem_cell in one more place.
2021-05-22 Marcelina Kościelnickakernel/rtlil: Extract some helpers for checking memory...
2021-03-30 Eddie Hungabc9: fix SCC issues (#2694)
2021-03-23 Marcelina Kościelnickartlil: Fix process memwr roundtrip.
2021-03-23 N. EngelhardtMerge pull request #2696 from nakengelhardt/guidelines
2021-03-23 Marcelina Kościelnickajson: Improve the "processes in module" message a bit.
2021-03-15 Marcelina Kościelnickajson: Add support for memories.
2021-03-12 whitequarkMerge pull request #2653 from zachjs/global-parameter
2021-03-11 whitequarkMerge pull request #2642 from whitequark/cxxrtl-noproc...
2021-03-10 Dan RavensloftReplace assert in xaiger with more useful error message
2021-03-09 whitequarkMerge pull request #2643 from zachjs/fix-param-no-defau...
2021-03-08 Marcelina KościelnickaAdd support for memory writes in processes.
2021-03-07 whitequarkcxxrtl: don't assert on edge sync rules tied to a constant.
2021-03-07 whitequarkcxxrtl: allow `always` sync rules in debug_eval.
2021-03-07 whitequarkMerge pull request #2626 from zachjs/param-no-default
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