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single-cycle mode fix on wb "wen" signal, must hold fully until ACKed
[c4m-jtag.git]
/
c4m
/
nmigen
/
jtag
/
tap.py
2021-04-16
Luke Kenneth Casso...
single-cycle mode fix on wb "wen" signal, must hold...
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2021-04-16
Luke Kenneth Casso...
underscore names on submodules possibly interfering...
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2021-04-08
Luke Kenneth Casso...
if no wb stall assume single-cycle mode
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2020-10-25
Luke Kenneth Casso...
resolve issue in coriolis2 with passing nmigen expressi...
24jan2021ls180
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2020-10-22
Luke Kenneth Casso...
correctly test length of IOs
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2020-10-22
Luke Kenneth Casso...
do not need to do IOconn
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2020-10-09
Luke Kenneth Casso...
code-cleanup / comments on JTAG IO
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2020-10-09
Luke Kenneth Casso...
add DMI interface to JTAG TAP
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2020-10-09
Luke Kenneth Casso...
fix wishbone optional stall
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2020-10-09
Luke Kenneth Casso...
add default features over-ride option to wishbone
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2020-10-09
Luke Kenneth Casso...
whitespace, comments
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2020-10-09
Luke Kenneth Casso...
whitespace cleanup
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2020-10-09
Luke Kenneth Casso...
whitespace cleanup
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2020-10-09
Luke Kenneth Casso...
nmigen explicit imports
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2020-01-06
Staf Verhaegen
Made nmigen code independent of VHDL code.
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2020-01-06
Staf Verhaegen
Force passing by name for TAP.add_shiftreg().
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2019-12-16
Staf Verhaegen
Specify names for TAP signals.
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2019-12-14
Staf Verhaegen
Made STATE and NEXT_STATE internal to c4m_jtag_tap_fsm.
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2019-12-14
Staf Verhaegen
Add top controller instance from nmigen code.
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2019-12-06
Staf Verhaegen
Simplify signal generation for TAP wishbone interfaces.
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2019-12-06
Staf Verhaegen
Use Elif for third m.next assignment.
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2019-12-06
Staf Verhaegen
Use Wishbone code from nmigen-soc.
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2019-12-06
Staf Verhaegen
Support JTAG bus with a reset signal.
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2019-12-06
Staf Verhaegen
Rework ShiftReg and Wishbone elaboration.
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2019-12-06
Staf Verhaegen
Use the JTAG Interface class as bus.
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2019-12-06
Staf Verhaegen
Get Wishbone from c4m lib.
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2019-12-06
Staf Verhaegen
Rename JTAG to TAP.
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2019-12-06
Staf Verhaegen
Renamed jtag.py -> tap.py.
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