| 2021-06-06 |
Luke Kenneth Casso... | argh, nsxlib cannot cope with 3 clocks! |
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| 2021-06-05 |
Luke Kenneth Casso... | sigh trying to find the right clock line |
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| 2021-06-05 |
Luke Kenneth Casso... | correct clock name for H-Tree in ls180 |
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| 2021-06-05 |
Luke Kenneth Casso... | set various clocks to use H-Tree |
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| 2021-04-24 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-04-22 |
Luke Kenneth Casso... | make placement of SRAMs optional, and PLL as well,... |
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| 2021-04-12 |
Luke Kenneth Casso... | another attempt to get 100% completed route |
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| 2021-04-11 |
Luke Kenneth Casso... | good grief, increasing ls180 core size to 70,000, 100... |
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| 2021-04-11 |
Luke Kenneth Casso... | increase core size to see if global routing can be... |
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| 2021-04-11 |
Luke Kenneth Casso... | crank up the numbers (again) |
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| 2021-04-11 |
Luke Kenneth Casso... | crank up the numbers to see if routing completion can... |
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| 2021-04-11 |
Luke Kenneth Casso... | increase katana tracks reserved |
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| 2021-03-29 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-03-29 |
Luke Kenneth Casso... | Revert "enable high fanout in ls180 experiment9 doDesig... |
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| 2021-03-29 |
Luke Kenneth Casso... | enable high fanout in ls180 experiment9 doDesign.py |
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| 2021-03-27 |
Luke Kenneth Casso... | add missing floorplan function call |
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| 2021-03-02 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-02-20 |
Luke Kenneth Casso... | increase core size to 50000 (DFF SRAMs) |
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| 2021-02-20 |
Luke Kenneth Casso... | expand core size to 28000 |
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| 2021-01-27 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2021-01-27 |
Jean-Paul Chaput | Pinmux loading is now integrated in Coriolis. |
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| 2020-12-04 |
Luke Kenneth Casso... | increase core size (again) to cope with DFFs currently... |
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| 2020-12-03 |
Luke Kenneth Casso... | increase size to 45,000 to cope with 3x extra SRAMs |
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| 2020-12-02 |
Luke Kenneth Casso... | increase size to 40,000 |
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| 2020-12-02 |
Luke Kenneth Casso... | begin random search for appropriate core size. start... |
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| 2020-11-13 |
Luke Kenneth Casso... | corona-core gap too small |
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| 2020-11-13 |
Luke Kenneth Casso... | increase core size yet again, shrink gap |
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| 2020-11-13 |
Luke Kenneth Casso... | increase core size, reduce corona gap again |
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| 2020-11-13 |
Luke Kenneth Casso... | increase chip size by 100, make chipSize closer to... |
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| 2020-11-12 |
Luke Kenneth Casso... | get core size big enough to fit pads along width |
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| 2020-11-12 |
Luke Kenneth Casso... | remove niolib io_in/out signal, no longer needed |
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| 2020-11-11 |
Luke Kenneth Casso... | adjust chip/core size to try to fit ls180 core/pads |
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| 2020-11-11 |
Luke Kenneth Casso... | add power/ground pads |
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| 2020-11-09 |
Luke Kenneth Casso... | add code comments for ioring-to-niolib conversion of... |
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| 2020-11-08 |
Luke Kenneth Casso... | start conversion of ls180 to new niolib |
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| 2020-09-19 |
Luke Kenneth Casso... | first attempt putting in litex pins instead of bare... |
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| 2020-08-07 |
Jean-Paul Chaput | Merge branch 'master' of ssh://libre-riscv.org:922... |
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| 2020-08-07 |
Jean-Paul Chaput | Use of CfgCache. Little beautificaton of doDesign.py |
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| 2020-08-05 |
Luke Kenneth Casso... | find semi-suitable width for spr0, add missing int... |
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| 2020-08-05 |
Luke Kenneth Casso... | workaround for spr bug |
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| 2020-08-05 |
Luke Kenneth Casso... | rename clk/rst to coresync_clk/rst, resize height of... |
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| 2020-08-05 |
Luke Kenneth Casso... | comment out pdecode2 block for now |
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| 2020-08-05 |
Luke Kenneth Casso... | add coriolis_setup, fix subckt numbering |
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| 2020-08-05 |
Luke Kenneth Casso... | add __main__ runner |
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| 2020-08-05 |
Luke Kenneth Casso... | indentation and add div0 to blockIssuer |
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| 2020-08-05 |
Luke Kenneth Casso... | substitute/indent to reduce to 80 char limit |
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| 2020-08-03 |
Jean-Paul Chaput | Fisrt attempt at floorplaning test_issuer. |
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projects / soclayout.git / history