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update libresoc.v to use sys_clk for main core
[soclayout.git]
/
experiments9
/
non_generated
/
full_core_4_4ksram_libresoc.v
2021-06-03
Luke Kenneth Casso...
update libresoc.v to use sys_clk for main core
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2021-05-27
Luke Kenneth Casso...
update libresoc.v
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2021-05-26
Luke Kenneth Casso...
clk_sel_i in TestIssuer was one bit not 2
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2021-05-26
Luke Kenneth Casso...
remove sram4k wb err (unused anyway)
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2021-05-25
Luke Kenneth Casso...
rename PLL out to out_v in test_issuer
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2021-05-24
Luke Kenneth Casso...
disappearing signal from pll, attempt to get it back
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2021-05-24
Luke Kenneth Casso...
rename cell to "real_pll" to avoid conflict with cell...
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2021-05-22
Luke Kenneth Casso...
correct PLL names
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2021-05-22
Luke Kenneth Casso...
re-add 4k sram
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2021-05-22
Luke Kenneth Casso...
update PLL to use submodule Instance
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2021-04-30
Luke Kenneth Casso...
enabling experiments9 new LibreSOCMem fake blackbox...
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2021-04-28
Luke Kenneth Casso...
name everything back to spblock_512w64b8w now that...
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2021-04-28
Luke Kenneth Casso...
rename spblock modules to just straight spblock_512w64b...
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2021-04-18
Luke Kenneth Casso...
argh, found the blackbox problem: yosys is "doing the...
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2021-04-18
Luke Kenneth Casso...
rename spblock_512w64b8w, and vco_test_ana for pll
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2021-04-18
Luke Kenneth Casso...
update ls180 sram4k
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2021-04-18
Luke Kenneth Casso...
add full core variant including 4k sram of ls180
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