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reorg of PLL, routed out into peripheral interconnect
[soclayout.git]
/
experiments9
/
non_generated
/
full_core_4_4ksram_litex_ls180_recon.v
2021-06-09
Luke Kenneth Casso...
reorg of PLL, routed out into peripheral interconnect
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2021-06-04
Jean-Paul Chaput
Merge branch 'master' of ssh://libre-riscv.org:922...
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2021-06-03
Luke Kenneth Casso...
rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk
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2021-06-03
Staf Verhaegen
Reroute clk so PLL output clock is used as sys_clk.
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2021-06-03
Staf Verhaegen
Duplicate file before patching for clock rerouting.
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projects / soclayout.git / history