git.libre-soc.org Git - soclayout.git/history - experiments9/non_generated/full_core_4_4ksram_litex_ls180

2021-06-09	Luke Kenneth Casso...	pll24_i renamed to clk_24_i	blob \| commitdiff \| raw
2021-06-09	Luke Kenneth Casso...	pllclk_o is renamed to pllclk_clk	blob \| commitdiff \| raw \| diff to current
2021-06-09	Luke Kenneth Casso...	use sys_pllclk_from_pad not sys_clk_from_pad	blob \| commitdiff \| raw \| diff to current
2021-06-09	Luke Kenneth Casso...	reorg of PLL, routed out into peripheral interconnect	blob \| commitdiff \| raw \| diff to current
2021-06-04	Jean-Paul Chaput	Merge branch 'master' of ssh://libre-riscv.org:922...	blob \| commitdiff \| raw \| diff to current
2021-06-03	Luke Kenneth Casso...	rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk	blob \| commitdiff \| raw \| diff to current
2021-06-03	Staf Verhaegen	Reroute clk so PLL output clock is used as sys_clk.	blob \| commitdiff \| raw \| diff to current
2021-06-03	Staf Verhaegen	Duplicate file before patching for clock rerouting.	blob \| commitdiff \| raw \| diff to current