build/sim: allow for arbitrary clocks generation using clockers
[litex.git] / litex / build / sim / core / sim.c
2020-08-03 Jędrzej Boczarbuild/sim: allow for arbitrary clocks generation using...
2020-08-03 Jędrzej Boczarbuild/sim: use a real timebase in the simulation
2020-05-27 enjoy-digitalMerge pull request #541 from antmicro/jboc/spd-read
2020-05-25 enjoy-digitalMerge pull request #539 from dayjaby/pr-fix_uart_startbit
2020-05-22 enjoy-digitalMerge pull request #535 from antmicro/arty-cv32e40p
2020-05-21 Florent Kermarrecbuild/sim: rename dut to sim (for consistency with...
2019-04-19 Sean CrossMerge branch 'master' of https://github.com/enjoy-digit...
2019-04-17 enjoy-digitalMerge pull request #162 from antmicro/full-conf-vexriscv
2019-04-17 enjoy-digitalMerge pull request #163 from gsomlo/gls-verilated-cmdargs
2019-04-17 Gabriel L. Somlobuild/sim/core: Initialize Verilator commandArgs
2019-01-11 Florent Kermarrecbuild/sim/core: fix coverage
2018-12-20 Tim AnsellMerge pull request #144 from mithro/nextpnr-migen-update
2018-12-20 Florent Kermarrecbuild/sim: handle verilog $finish and if coverage is...
2018-11-26 enjoy-digitalMerge pull request #128 from mithro/small-fix
2018-11-20 Florent Kermarrecbuild/sim/verilator: add trace parameter to enable...
2017-06-28 Florent Kermarreclitex/build/sim: rename c functions from lambdasim...
2017-06-28 Florent Kermarreclitex/build/sim: small cleanup
2017-06-28 Pierre-Olivier Vauboinlitex/build/sim: introduce new simulator with modules...