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Formally release this version of Aquila under the GNU LGPLv3+
[microwatt.git]
/
microwatt.core
2021-02-08
Michael Neuling
Merge pull request #269 from paulusmack/pipeline
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2021-02-08
Michael Neuling
Merge pull request #268 from paulusmack/btc
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2021-01-18
Paul Mackerras
core: Track CR hazards and bypasses using tags
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2021-01-18
Paul Mackerras
core: Track GPR hazards using tags that propagate throu...
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2021-01-18
Paul Mackerras
fetch1: Implement a simple branch target cache
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2020-09-17
Michael Neuling
Merge pull request #245 from paulusmack/fpu
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2020-09-03
Paul Mackerras
core: Add framework for an FPU
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2020-09-03
Paul Mackerras
core: Add support for floating-point loads and stores
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2020-08-13
Michael Neuling
Merge pull request #235 from paulusmack/master
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2020-08-13
Michael Neuling
Merge pull request #236 from ozbenh/targets
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2020-08-07
Boris Shingarov
fpga: Add support for Genesys2
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2020-08-07
Benjamin Herrenschmidt
acorn: Add support for the Acorn CLE 215+
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2020-08-06
Paul Mackerras
Add random number generator and implement the darn...
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2020-07-09
Michael Neuling
Merge pull request #228 from ozbenh/misc
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2020-07-08
Benjamin Herrenschmidt
corefile/nexys_video: Parameter fixes
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2020-06-30
Paul Mackerras
Merge pull request #206 from Jbalkind/icachecleanup
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2020-06-29
Michael Neuling
Merge pull request #213 from ozbenh/uart16550
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2020-06-29
Michael Neuling
Merge pull request #212 from ozbenh/liteeth
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2020-06-25
Benjamin Herrenschmidt
uart: Make 16550 the default
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2020-06-23
Benjamin Herrenschmidt
uart: Import and hook up opencore 16550 compatible...
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2020-06-23
Benjamin Herrenschmidt
liteeth: Hook up LiteX LiteEth ethernet controller
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2020-06-19
Michael Neuling
Merge pull request #208 from paulusmack/faster
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2020-06-16
Paul Mackerras
fpga: Add a xilinx_specific fileset to microwatt.core
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2020-06-16
Paul Mackerras
Make LOG_LENGTH configurable per FPGA variant
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2020-06-13
Paul Mackerras
multiply: Use DSP48 slices for multiplication on Xilinx...
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2020-06-13
Paul Mackerras
core: Remove fetch2 pipeline stage
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2020-06-13
Paul Mackerras
Merge pull request #204 from ozbenh/spi
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2020-06-12
Benjamin Herrenschmidt
spi: Add SPI Flash controller
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2020-06-05
Paul Mackerras
Merge pull request #191 from ozbenh/litedram
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2020-06-05
Benjamin Herrenschmidt
litedram: Add an L2 cache with store queue
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2020-06-05
Benjamin Herrenschmidt
litedram: Add support for booting without BRAM
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2020-06-03
Paul Mackerras
Merge pull request #168 from shenki/flash-arty
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2020-05-19
Anton Blanchard
Merge branch 'master' into litedram
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2020-05-19
Anton Blanchard
Merge pull request #176 from antonblanchard/console...
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2020-05-19
Anton Blanchard
Merge pull request #174 from antonblanchard/yosys-fixes
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2020-05-18
Anton Blanchard
Merge pull request #169 from paulusmack/mmu
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2020-05-14
Paul Mackerras
Merge branch 'mmu'
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2020-05-14
Anton Blanchard
Merge pull request #170 from antonblanchard/litedram
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2020-05-08
Benjamin Herrenschmidt
syscon: Add syscon registers
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2020-05-08
Benjamin Herrenschmidt
fpga: Hookup nexys-video to litedram
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2020-05-08
Benjamin Herrenschmidt
fpga: Hookup Arty to litedram
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2020-05-08
Paul Mackerras
Add framework for implementing an MMU
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2020-05-08
Benjamin Herrenschmidt
litedram: Add basic support for LiteX LiteDRAM
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2020-05-08
Benjamin Herrenschmidt
Change default frequency to 100Mhz
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2020-05-08
Benjamin Herrenschmidt
xics: Add missing fusesoc core file
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2020-04-16
Anton Blanchard
Merge pull request #159 from shenki/fusesoc-ram-16k
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2020-04-15
Joel Stanley
Set default RAM to be 16K in microwatt.core
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2019-11-15
Anton Blanchard
Merge pull request #118 from antonblanchard/bus-pipeline
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2019-10-30
Benjamin Herrenschmidt
ram: Rework main RAM interface
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2019-10-30
Benjamin Herrenschmidt
Add option to not flatten hierarchy
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2019-10-25
Anton Blanchard
Merge pull request #113 from mikey/exec-sim-remove
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2019-10-25
Anton Blanchard
Merge pull request #114 from antonblanchard/dcache
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2019-10-23
Benjamin Herrenschmidt
dcache: Add a dcache
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2019-10-16
Anton Blanchard
Merge pull request #105 from paulusmack/writeback
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2019-10-15
Paul Mackerras
Remove execute2 stage
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2019-10-15
Anton Blanchard
Merge pull request #103 from paulusmack/divider
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2019-10-15
Anton Blanchard
Merge pull request #102 from antonblanchard/gpr-hazard-5-c
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2019-10-15
Anton Blanchard
Add CR hazard detection
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2019-10-15
Anton Blanchard
Merge pull request #101 from antonblanchard/gpr-hazard-5-b
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2019-10-14
Anton Blanchard
Add GPR hazard detection
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2019-10-14
Anton Blanchard
Merge pull request #100 from antonblanchard/gpr-hazard-5-a
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2019-10-14
Anton Blanchard
Separate issue control into its own unit
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2019-10-11
Anton Blanchard
Merge pull request #84 from classilla/master
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2019-10-11
Anton Blanchard
Merge pull request #89 from mikey/gitignore
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2019-10-10
Anton Blanchard
Merge pull request #87 from antonblanchard/cmod-a7...
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2019-10-10
Anton Blanchard
Fix cmod-a7 frequency
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2019-10-10
Anton Blanchard
Merge pull request #79 from deece/uart_address
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2019-10-09
Anton Blanchard
Merge pull request #83 from paulusmack/logical
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2019-10-09
Anton Blanchard
Merge pull request #81 from antonblanchard/logical
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2019-10-09
Anton Blanchard
Merge pull request #82 from antonblanchard/icache-set...
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2019-10-08
Paul Mackerras
execute: Consolidate count-leading/trailing-zeroes...
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2019-10-08
Anton Blanchard
Consolidate logical instructions
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2019-10-08
Benjamin Herrenschmidt
icache: Set associative icache
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2019-10-08
Benjamin Herrenschmidt
plru: Add a simple PLRU module
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2019-10-07
Anton Blanchard
Merge pull request #78 from paulusmack/new-decode
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2019-10-07
Paul Mackerras
Add a rotate/mask/shift unit and use it in execute1
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2019-09-30
Anton Blanchard
Merge pull request #77 from antonblanchard/timing
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2019-09-30
Anton Blanchard
Merge pull request #76 from antonblanchard/misc
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2019-09-30
Benjamin Herrenschmidt
Improve PLL/MMCM clocks configuration
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2019-09-30
Benjamin Herrenschmidt
corefile: Remove duplicate wishbone_debug_master
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2019-09-30
Benjamin Herrenschmidt
fpga: Arty A7's don't need multiple filesets
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2019-09-28
Anton Blanchard
Merge pull request #75 from paulusmack/master
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2019-09-27
Paul Mackerras
fpga: Add definitions for Arty A7-100 board
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2019-09-24
Anton Blanchard
Merge branch 'divider' of https://github.com/paulusmack...
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2019-09-24
Anton Blanchard
Merge pull request #69 from antonblanchard/debug-module
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2019-09-23
Anton Blanchard
Add core_debug.vhdl to fusesoc configs
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2019-09-23
Paul Mackerras
Add a divider unit and a testbench for it
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2019-09-20
Benjamin Herrenschmidt
Wishbone debug module
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2019-09-20
Benjamin Herrenschmidt
Add a debug (DMI) bus and a JTAG interface to it on...
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2019-09-12
Anton Blanchard
Merge pull request #49 from antonblanchard/icache-2
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2019-09-12
Anton Blanchard
Add a simple direct mapped icache
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2019-09-10
Benjamin Herrenschmidt
Share soc.vhdl between FPGA and sim
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2019-09-10
Benjamin Herrenschmidt
Pass wishbone record to bram memory module
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2019-09-10
Benjamin Herrenschmidt
Split FPGA toplevel from soc
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2019-09-08
Anton Blanchard
Merge pull request #19 from antonblanchard/cmod-a7
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2019-09-08
Anton Blanchard
Cmod A7-35 support
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2019-09-08
Anton Blanchard
Merge pull request #20 from antonblanchard/reset-rework2
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2019-09-07
Anton Blanchard
Rework SOC reset
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2019-09-03
Anton Blanchard
Merge pull request #16 from antonblanchard/decode2_rework2
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2019-09-03
Anton Blanchard
Rework decode2
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