| 2020-10-25 |
whitequark | back.{verilog,rtlil}: adjust $verilog_initial_trigger... |
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| 2020-08-26 |
whitequark | back.rtlil: do not squash empty modules. |
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| 2020-07-22 |
whitequark | back.rtlil: lower maximum accepted wire size. |
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| 2020-07-15 |
whitequark | back.rtlil: fix guard for division by zero. |
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| 2020-05-19 |
whitequark | back.rtlil: handle signed and large Instance parameters... |
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| 2020-04-28 |
whitequark | back.rtlil: fix incorrect escaping of signed parameters. |
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| 2020-04-16 |
anuejn | hdl.rec: make Record inherit from UserValue. working_23jun2020 |
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| 2020-04-15 |
whitequark | back.rtlil: translate enum decoders to Yosys enum attri... |
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| 2020-04-13 |
whitequark | back.rtlil: don't emit connections to zero width ports. |
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| 2020-04-13 |
whitequark | back.rtlil: refuse to create extremely large wires. |
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| 2020-04-13 |
whitequark | back.rtlil: fix expansion of Part() for partial dummy... |
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| 2020-04-13 |
whitequark | back.rtlil: fix legalization of Part() with stride. |
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| 2020-04-13 |
whitequark | Clarify a few comments. NFC. |
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| 2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
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| 2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support. |
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| 2020-01-31 |
whitequark | back.rtlil: don't emit wires for empty signals. |
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| 2020-01-01 |
whitequark | back.rtlil: do not consider unreachable array elements... |
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| 2019-11-27 |
whitequark | back.rtlil: infer bit width for instance parameters. |
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| 2019-11-18 |
whitequark | back.rtlil: extend shorter operand of a binop when... |
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| 2019-10-28 |
whitequark | back.verilog: remove $verilog_initial_trigger after... |
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| 2019-10-26 |
whitequark | back.rtlil: avoid exponential behavior when legalizing... |
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| 2019-10-26 |
whitequark | back.rtlil: fix lowering of Part() on LHS to account... |
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| 2019-10-13 |
whitequark | {,_}tools→{,_}utils |
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| 2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop. |
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| 2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
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| 2019-10-12 |
Jean-François Nguyen | back.rtlil: fix DeprecationWarning. NFC. |
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| 2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor... |
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| 2019-10-11 |
whitequark | hdl.ast: Operator.{op→operator} |
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| 2019-10-06 |
whitequark | back.rtlil: don't crash legalizing values with no branches. |
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| 2019-10-04 |
whitequark | back.rtlil: avoid unsoundness for division by zero. |
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| 2019-10-02 |
whitequark | back.rtlil: don't cache wires for legalized switch... |
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| 2019-10-02 |
whitequark | back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow... |
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| 2019-10-02 |
whitequark | back.rtlil: it is not necessary to match binop operand... |
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| 2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
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| 2019-09-24 |
whitequark | back.rtlil: fix handling of certain nested arrays. |
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| 2019-09-23 |
whitequark | back.rtlil: give predictable names to anonymous subfrag... |
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| 2019-09-20 |
whitequark | hdl.ast: rename `nbits` to `width`. |
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| 2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
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| 2019-09-11 |
whitequark | back: return name map from convert_fragment(). |
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| 2019-09-03 |
whitequark | hdl.ast,back.rtlil: implement Cover. |
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| 2019-08-31 |
whitequark | hdl.cd: add negedge clock domains. |
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| 2019-08-22 |
whitequark | back.rtlil: print real parameters with maximum precision. |
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| 2019-08-22 |
Darrell Harmon | back.rtlil: add support for real (float) parameters... |
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| 2019-08-19 |
whitequark | back.{rtlil,verilog}: split convert_fragment() off... |
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| 2019-08-15 |
whitequark | hdl.ast: implement Initial. |
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| 2019-08-04 |
whitequark | back.rtlil: use a dummy wire, not 'x, when assigning... |
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| 2019-08-03 |
whitequark | back.rtlil: actually match shape of left hand side. |
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| 2019-08-03 |
whitequark | back.rtlil: fix sim-synth mismatch with assigns followi... |
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| 2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word... |
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| 2019-08-03 |
whitequark | hdl.ast, back.rtlil: add source locations to anonymous... |
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| 2019-07-09 |
whitequark | back.rtlil: add decodings to cases when switching on... |
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| 2019-07-09 |
whitequark | hdl.{ast,dsl},back.rtlil: track source locations for... |
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| 2019-07-08 |
whitequark | build.{dsl,res}: allow platform-dependent attributes... |
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| 2019-07-08 |
whitequark | back.rtlil: don't name-prefix signals connected to... |
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| 2019-07-08 |
whitequark | back.rtlil: ignore empty source locations. |
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| 2019-07-08 |
whitequark | back.rtlil: attach source locations to switches, not... |
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| 2019-07-08 |
whitequark | back.rtlil: use a more principled approach to attribute... |
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| 2019-07-03 |
whitequark | back.rtlil: emit \src attributes for processes via... |
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| 2019-07-02 |
whitequark | back.rtlil: emit \sig$next wires instead of \$next... |
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| 2019-07-02 |
whitequark | back.rtlil: do not emit $next wires for comb signals. |
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| 2019-07-01 |
whitequark | back.rtlil: fix Array regression in 32446831. |
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| 2019-06-28 |
whitequark | hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case... |
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| 2019-06-28 |
whitequark | hdl.ir, back.rtlil: allow specifying attributes on... |
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| 2019-06-11 |
whitequark | back.rtlil: mask memory init values. |
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| 2019-05-26 |
whitequark | back.rtlil: allow specifying platform for convert(). |
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| 2019-05-13 |
whitequark | back.rtlil: assign undriven signals to their reset... |
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| 2019-04-22 |
whitequark | hdl.ir: rework named port handling for Instances. |
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| 2019-04-21 |
whitequark | back.rtlil: emit `nmigen.hierarchy` attribute. |
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| 2019-04-21 |
whitequark | back.rtlil: only expand legalized values in Array/Part... |
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| 2019-04-20 |
whitequark | back.rtlil: allow record slices on LHS. |
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| 2019-03-28 |
whitequark | back.rtlil: fix off-by-one in Part legalization. |
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| 2019-01-26 |
whitequark | back.rtlil: accept ast.Const as cell parameter. |
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| 2019-01-26 |
whitequark | back.rtlil: accept any elaboratable, not just fragments. |
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| 2019-01-19 |
whitequark | hdl.ast: give Assert and Assume their own src_loc. |
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| 2019-01-18 |
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once. |
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| 2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer. |
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| 2019-01-16 |
whitequark | back.rtlil: slightly nicer naming for $next signals... |
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| 2019-01-16 |
whitequark | back.rtlil: rename \sig$next to $next$sig. |
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| 2019-01-15 |
whitequark | Unbreak 655d02d5. |
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| 2019-01-15 |
William D. Jones | back.rtlil: Generate $anyconst and $anyseq cells. |
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| 2019-01-02 |
whitequark | back.rtlil: translate empty slices correctly. |
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| 2019-01-02 |
William D. Jones | back.rtlil: Generate RTLIL for Assert/Assume statements. |
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| 2019-01-01 |
whitequark | back.rtlil: fix typo. |
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| 2018-12-31 |
whitequark | back.rtlil: match shape of Array elements to ArrayProxy... |
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| 2018-12-31 |
whitequark | back.rtlil: fix typo. |
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| 2018-12-28 |
whitequark | hdl.rec: add basic record support. |
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| 2018-12-26 |
whitequark | back.rtlil: clarify $verilog_initial_trigger behavior... |
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| 2018-12-24 |
whitequark | back.rtlil: unbreak d47c1f8a. |
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| 2018-12-24 |
whitequark | back.rtlil: use one $meminit cell, not one per word. |
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| 2018-12-24 |
whitequark | hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. |
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| 2018-12-24 |
whitequark | hdl.xfrm: implement SwitchCleaner, for pruning empty... |
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| 2018-12-24 |
whitequark | back.rtlil: always output negative values as two's... |
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| 2018-12-23 |
whitequark | back.rtlil: emit dummy logic to work around Verilog... |
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| 2018-12-23 |
whitequark | back.rtlil: do not translate empty fragments. |
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| 2018-12-23 |
whitequark | back.rtlil: only translate switch tests once. |
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| 2018-12-23 |
whitequark | back.rtlil: fix swapped operands in mux codegen. |
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| 2018-12-22 |
whitequark | back.rtlil: split processes as finely as possible. |
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| 2018-12-22 |
whitequark | back.rtlil: remove useless condition. NFC. |
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| 2018-12-22 |
whitequark | back.rtlil: always initialize the entire memory. |
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| 2018-12-21 |
whitequark | back.rtlil: more consistent prefixing for subfragment... |
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