projects
/
nmigen.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
back.rtlil: do not translate empty fragments.
[nmigen.git]
/
nmigen
/
back
/
rtlil.py
2018-12-23
whitequark
back.rtlil: do not translate empty fragments.
blob
|
commitdiff
|
raw
2018-12-23
whitequark
back.rtlil: only translate switch tests once.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-23
whitequark
back.rtlil: fix swapped operands in mux codegen.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-22
whitequark
back.rtlil: split processes as finely as possible.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-22
whitequark
back.rtlil: remove useless condition. NFC.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-22
whitequark
back.rtlil: always initialize the entire memory.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-21
whitequark
back.rtlil: more consistent prefixing for subfragment...
blob
|
commitdiff
|
raw
|
diff to current
2018-12-21
whitequark
back.rtlil: implement memories.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-21
whitequark
back.rtlil: explicitly pad constants with zeroes.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-21
whitequark
back.rtlil: fix translation of Cat.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-20
whitequark
ir: allow non-Signals in Instance ports.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-17
whitequark
fhdl.ir: add black-box fragments, fragment parameters...
blob
|
commitdiff
|
raw
|
diff to current
2018-12-17
whitequark
hdl, back: add and use SignalSet/SignalDict.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-17
whitequark
back.rtlil: update for Yosys master.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-17
whitequark
back.rtlil: implement Array.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-17
whitequark
back.rtlil: implement Part.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: handle reset_less domains.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: extract _StatementCompiler. NFC.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: simplify. NFC.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: properly escape strings in attributes.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: prepare for Yosys sigspec slicing improvements.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: avoid illegal slices.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: use slicing to match shape when reducing...
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: don't emit a slice if all bits are used.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: reorganize value compiler into LHS/RHS.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
back.rtlil: fix naming. NFC.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-16
whitequark
hdl.xfrm: separate AST traversal from AST identity...
blob
|
commitdiff
|
raw
|
diff to current
2018-12-15
whitequark
Rename fhdl→hdl, genlib→lib.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-15
whitequark
fhdl.ast, back.pysim: implement shifts.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.ir: move Fragment prepare logic from back.rtlil.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.ir: record port direction explicitly.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl, back: trace and emit source locations of values.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: never give subfragment cells names starting...
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.ir: implement clock domain propagation.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.ir: remove iter_domains().
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl: cd_name→domain.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.cd: rename ClockDomain.{reset→rst}.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: fix swapped operands in sync assign.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: explain logic for CD reset insertion.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: explicitly set the top module.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.ir: explain how port enumeration works.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: explain how RTLIL conversion works.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: give clocks and resets nicer names.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
back.rtlil: match shape of $mux ports A/B/Y.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-13
whitequark
fhdl.ast: bits_sign→shape.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-12
whitequark
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-12
whitequark
fhdl.ast.Signal: implement attrs field.
blob
|
commitdiff
|
raw
|
diff to current
2018-12-12
whitequark
ClockDomain.{rst→reset}, for consistency with ResetInse...
blob
|
commitdiff
|
raw
|
diff to current
2018-12-12
whitequark
Initial commit.
blob
|
commitdiff
|
raw
|
diff to current
projects / nmigen.git / history