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back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.
[nmigen.git]
/
nmigen
/
back
/
verilog.py
2020-10-25
whitequark
back.{verilog,rtlil}: adjust $verilog_initial_trigger...
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2020-08-27
whitequark
back.verilog: use `proc -nomux` if it is available.
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2020-08-26
whitequark
back.verilog: omit Verilog initial trigger only if...
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2020-07-02
whitequark
_yosys→_toolchain.yosys
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2020-06-14
whitequark
back.verilog: refactor Yosys script generation. NFCI.
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2020-06-11
whitequark
_yosys: translate Yosys warnings to Python warnings.
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2020-06-11
whitequark
back.verilog: remove unused imports. NFC.
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2020-05-22
whitequark
back.verilog: fall back to nmigen_yosys package.
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2020-04-23
Teguh Hofstee
back.verilog: add workaround for evaluation Verific...
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2020-04-22
Teguh Hofstee
back.verilog: make Yosys version check compatible with...
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2019-10-28
whitequark
back.verilog: remove $verilog_initial_trigger after...
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2019-10-16
Sebastien Bourdeauducq
verilog: fix yosys version error message
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2019-10-16
whitequark
back.verilog: fix Yosys version check.
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2019-10-10
whitequark
vendor.intel: add Quartus support.
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2019-09-24
whitequark
build.plat: strip internal attributes from Verilog...
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2019-09-11
whitequark
back: return name map from convert_fragment().
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2019-08-31
Emily
_toolchain,build.plat,vendor.*: add required_tools...
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2019-08-28
whitequark
_toolchain: new module, for injecting dependencies...
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2019-08-26
whitequark
back.verilog: bump Yosys version requirement to 0.9.
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2019-08-19
whitequark
back.verilog: parse output of `yosys -V`.
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2019-08-19
whitequark
back.{rtlil,verilog}: split convert_fragment() off...
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2019-07-09
whitequark
back.verilog: run proc_prune for much cleaner output.
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2019-04-22
whitequark
back.verilog: allow stripping the src attribute, for...
working
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2019-01-13
whitequark
back.verilog: better error message if Yosys is not...
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2019-01-08
whitequark
back.verilog: remove undriven check.
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2018-12-22
whitequark
back.verilog: do not rename internal signals.
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2018-12-21
whitequark
hdl.mem: tie rdport.en high for asynchronous or transpa...
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2018-12-21
whitequark
back.rtlil: implement memories.
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2018-12-13
whitequark
back.verilog: remove debug code.
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2018-12-13
whitequark
compat.genlib.fsm: import/wrap Migen code.
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2018-12-13
whitequark
back.verilog: detect undriven public wires using Yosys.
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2018-12-12
whitequark
Initial commit.
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