git.libre-soc.org Git - nmigen.git/history

2019-04-22	whitequark	back.verilog: allow stripping the src attribute, for... working	blob \| commitdiff \| raw
2019-01-13	whitequark	back.verilog: better error message if Yosys is not...	blob \| commitdiff \| raw \| diff to current
2019-01-08	whitequark	back.verilog: remove undriven check.	blob \| commitdiff \| raw \| diff to current
2018-12-22	whitequark	back.verilog: do not rename internal signals.	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: tie rdport.en high for asynchronous or transpa...	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	back.rtlil: implement memories.	blob \| commitdiff \| raw \| diff to current
2018-12-13	whitequark	back.verilog: remove debug code.	blob \| commitdiff \| raw \| diff to current
2018-12-13	whitequark	compat.genlib.fsm: import/wrap Migen code.	blob \| commitdiff \| raw \| diff to current
2018-12-13	whitequark	back.verilog: detect undriven public wires using Yosys.	blob \| commitdiff \| raw \| diff to current
2018-12-12	whitequark	Initial commit.	blob \| commitdiff \| raw \| diff to current