git.libre-soc.org Git - nmigen.git/history

2020-09-17	Jean-François Nguyen	hdl.mem: document ReadPort and WritePort.	blob \| commitdiff \| raw
2020-07-30	Adam Greig	hdl.mem: cast reset value for transparent read ports...	blob \| commitdiff \| raw \| diff to current
2020-04-05	whitequark	hdl.mem: fix source location of ReadPort.en.	blob \| commitdiff \| raw \| diff to current
2020-02-06	whitequark	hdl.mem: add synthesis attribute support.	blob \| commitdiff \| raw \| diff to current
2020-02-06	whitequark	hdl.mem: document Memory.	blob \| commitdiff \| raw \| diff to current
2019-12-15	whitequark	hdl.mem: fix src_loc_at in ReadPort, WritePort.	blob \| commitdiff \| raw \| diff to current
2019-10-26	whitequark	test: use `#nmigen:` magic comment instead of monkey...	blob \| commitdiff \| raw \| diff to current
2019-10-11	whitequark	hdl.ast: deprecate Signal.{range,enum}.	blob \| commitdiff \| raw \| diff to current
2019-10-11	whitequark	Consistently use {!r}, not '{!r}' in diagnostics.	blob \| commitdiff \| raw \| diff to current
2019-09-28	whitequark	hdl.mem: remove WritePort(priority=) argument.	blob \| commitdiff \| raw \| diff to current
2019-09-23	whitequark	hdl.mem,lib.fifo: use keyword-only arguments for memory...	blob \| commitdiff \| raw \| diff to current
2019-09-23	whitequark	hdl.mem: simplify. NFC.	blob \| commitdiff \| raw \| diff to current
2019-09-20	whitequark	hdl.mem: use 1 as reset value for ReadPort.en.	blob \| commitdiff \| raw \| diff to current
2019-09-20	whitequark	hdl.ast: rename `nbits` to `width`.	blob \| commitdiff \| raw \| diff to current
2019-09-12	whitequark	hdl.mem: use keyword-only arguments as appropriate.	blob \| commitdiff \| raw \| diff to current
2019-09-08	whitequark	hdl.mem,lib,examples: use Signal.range().	blob \| commitdiff \| raw \| diff to current
2019-07-08	whitequark	hdl.{dsl,mem,xfrm}: inject appropriate source locations.	blob \| commitdiff \| raw \| diff to current
2019-07-02	whitequark	hdl.mem: fix naming of registers inside unnamed memories.	blob \| commitdiff \| raw \| diff to current
2019-07-01	whitequark	hdl.mem: use read_port(domain="comb") for asynchronous...	blob \| commitdiff \| raw \| diff to current
2019-06-11	whitequark	hdl.mem: coerce memory init values to integers.	blob \| commitdiff \| raw \| diff to current
2019-04-21	whitequark	hdl.ir: detect elaboratables that are created but not...	blob \| commitdiff \| raw \| diff to current
2019-03-03	whitequark	tracer: factor out get_var_name(default=).	blob \| commitdiff \| raw \| diff to current
2019-01-26	whitequark	hdl.ir: rename .get_fragment() to .elaborate().	blob \| commitdiff \| raw \| diff to current
2019-01-01	whitequark	hdl.mem: add DummyPort, for testing and verification.	blob \| commitdiff \| raw \| diff to current
2018-12-28	whitequark	tracer: factor out get_src_loc().	blob \| commitdiff \| raw \| diff to current
2018-12-27	whitequark	hdl.mem: add missing __all__.	blob \| commitdiff \| raw \| diff to current
2018-12-24	whitequark	hdl.mem: allow omitting memory simulation logic.	blob \| commitdiff \| raw \| diff to current
2018-12-22	whitequark	hdl.mem: allow changing init value after creating memory.	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: use more informative signal naming for ports.	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: ensure transparent read port model has correct...	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: use different naming for array signals.	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: add simulation model for memory.	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: add tests for all error conditions.	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: tie rdport.en high for asynchronous or transpa...	blob \| commitdiff \| raw \| diff to current
2018-12-21	whitequark	hdl.mem: implement memories.	blob \| commitdiff \| raw \| diff to current

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