| 2020-07-28 |
Jacob Graves | tests: fix remove unnecessary workaround for some unitt... |
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| 2020-07-07 |
whitequark | back.pysim: synchronize waveform writing with cxxrtl. |
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| 2020-07-07 |
whitequark | Remove everything deprecated in nmigen 0.2. |
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| 2020-07-02 |
whitequark | test: remove FHDLTestCase.assertRaisesRegex. |
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| 2020-05-20 |
whitequark | hdl.ast: add const-shift operations. |
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| 2020-04-13 |
Dan Ravensloft | hdl.ast: add Value.{rotate_left,rotate_right}. |
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| 2020-03-22 |
whitequark | hdl.ast: implement abs() on values. |
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| 2020-03-15 |
Stuart Olsen | back.pysim: implement modulus operator. |
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| 2020-02-19 |
whitequark | back.pysim: fix RHS codegen for Cat() and Repl(...... |
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| 2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
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| 2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value. |
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| 2019-11-28 |
whitequark | back.pysim: redesign the simulator. |
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| 2019-10-13 |
whitequark | {,_}tools→{,_}utils |
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| 2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
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| 2019-10-11 |
whitequark | Rename remaining `wrap` methods to `cast`. |
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| 2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics. |
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| 2019-10-11 |
whitequark | hdl.ast: Value.{wrap→cast} |
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| 2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
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| 2019-09-20 |
whitequark | hdl.mem: use 1 as reset value for ReadPort.en. |
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| 2019-09-20 |
whitequark | back.pysim: fix simulation of Value.xor(). |
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| 2019-09-13 |
whitequark | hdl.ast: add Value.xor, mapping to $reduce_xor. |
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| 2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
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| 2019-08-23 |
whitequark | back.pysim: implement sim.add_clock(if_exists=True). locally_working |
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| 2019-08-23 |
whitequark | back.pysim: don't crash when trying to drive a nonexist... |
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| 2019-08-19 |
whitequark | build.plat, hdl.ir: coordinate missing domain creation. |
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| 2019-08-03 |
whitequark | hdl.ir: call back from Fragment.prepare if a clock... |
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| 2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word... |
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| 2019-07-01 |
whitequark | hdl.mem: use read_port(domain="comb") for asynchronous... |
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| 2019-06-11 |
whitequark | back.pysim: check for a clock being added twice. |
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| 2019-03-28 |
whitequark | test_sim: add missing add_process(). |
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| 2019-01-26 |
whitequark | hdl.ir: rename .get_fragment() to .elaborate(). |
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| 2019-01-25 |
whitequark | back.pysim: fix behavior of initial cycle for sync... |
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| 2019-01-21 |
whitequark | back.pysim: wake up processes before ever committing... |
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| 2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell. |
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| 2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals. |
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| 2018-12-29 |
whitequark | back.pysim: warn if simulation is not run. |
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| 2018-12-28 |
whitequark | hdl.rec: add basic record support. |
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| 2018-12-21 |
whitequark | hdl.mem: ensure transparent read port model has correct... |
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| 2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
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| 2018-12-21 |
whitequark | hdl.mem: add simulation model for memory. |
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| 2018-12-18 |
whitequark | back.pysim: implement *. |
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| 2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors. |
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| 2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
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| 2018-12-15 |
whitequark | test.sim: generalize assertOperator. NFC. |
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| 2018-12-15 |
whitequark | back.pysim: implement Part. |
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| 2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
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| 2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
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| 2018-12-15 |
whitequark | pyback.sim: test Slice, Cat, Repl. |
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| 2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
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| 2018-12-14 |
whitequark | fhdl.ir: Fragment.{drive→add_driver} |
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| 2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
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| 2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
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projects / nmigen.git / history