2020-10-15 |
whitequark | tests: keep comments up to date. NFC. |
tree | commitdiff |
2020-08-27 |
whitequark | nmigen.test.utils: restore FHDLTestCase to gracefully... |
tree | commitdiff |
2020-08-27 |
whitequark | tests: move out of the main package. |
tree | commitdiff |
2020-08-26 |
whitequark | hdl.ast: avoid unnecessary sign padding in ArrayProxy. |
tree | commitdiff |
2020-08-26 |
whitequark | sim._pyrtl: fix miscompilation of -(Const(0b11, 2)... |
tree | commitdiff |
2020-08-26 |
whitequark | lib.cdc: in AsyncFFSynchronizer(), rename domain= to... |
tree | commitdiff |
2020-08-15 |
awygle | lib.fifo: add `r_level` and `w_level` to all FIFOs |
tree | commitdiff |
2020-07-31 |
whitequark | build,vendor: never carry around parts of differential... |
tree | commitdiff |
2020-07-28 |
Jean THOMAS | nmigen.lib.scheduler: add RoundRobin. |
tree | commitdiff |
2020-07-28 |
Jacob Graves | tests: fix remove unnecessary workaround for some unitt... |
tree | commitdiff |
2020-07-07 |
awygle | hdl.ast: don't inherit Shape from NamedTuple. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: synchronize waveform writing with cxxrtl. |
tree | commitdiff |
2020-07-07 |
whitequark | Remove everything deprecated in nmigen 0.2. |
tree | commitdiff |
2020-07-02 |
whitequark | test: remove FHDLTestCase.assertRaisesRegex. |
tree | commitdiff |
2020-06-30 |
whitequark | Add (heavily work in progress) documentation. |
tree | commitdiff |
2020-06-28 |
whitequark | lib.cdc: update PulseSynchronizer to follow conventions. |
tree | commitdiff |
2020-06-11 |
whitequark | test: fix example test after commit a7b8ced9. |
tree | commitdiff |
2020-06-06 |
Adam Greig | hdl.xfrm: preserve allow_reset_less when transforming... |
tree | commitdiff |
2020-06-05 |
Shawn Anastasio | hdl.rec: preserve shapes when constructing a layout. |
tree | commitdiff |
2020-05-20 |
whitequark | hdl.ast: add const-shift operations. |
tree | commitdiff |
2020-05-19 |
whitequark | hdl.dsl: check for unique domain name. |
tree | commitdiff |
2020-04-24 |
awygle | hdl.ir: typecheck `convert(ports=)` more carefully. |
tree | commitdiff |
2020-04-16 |
anuejn | hdl.rec: make Record inherit from UserValue. working_23jun2020 |
tree | commitdiff |
2020-04-13 |
Dan Ravensloft | hdl.ast: add Value.{rotate_left,rotate_right}. |
tree | commitdiff |
2020-04-12 |
whitequark | hdl.rec: improve repr() for Layout. |
tree | commitdiff |
2020-04-12 |
whitequark | hdl.ast: improve repr() for Shape. |
tree | commitdiff |
2020-04-02 |
Jacob Lifshay | Add support for using non-compat Elaboratable instances... |
tree | commitdiff |
2020-03-22 |
whitequark | hdl.ast: implement abs() on values. |
tree | commitdiff |
2020-03-15 |
Stuart Olsen | back.pysim: implement modulus operator. |
tree | commitdiff |
2020-03-14 |
awygle | Correctly handle resets in AsyncFIFO. |
tree | commitdiff |
2020-03-08 |
awygle | lib.cdc: extract AsyncFFSynchronizer. |
tree | commitdiff |
2020-02-19 |
whitequark | back.pysim: fix RHS codegen for Cat() and Repl(...... |
tree | commitdiff |
2020-02-16 |
awygle | nmigen.lib.cdc: port PulseSynchronizer. |
tree | commitdiff |
2020-02-07 |
whitequark | test_build_res: fix after commit 3e2ecdf2. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
tree | commitdiff |
2020-02-06 |
whitequark | test_lib_fifo: define all referenced FSM states. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.dsl: make referencing undefined FSM states an error. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.ir: type check ports. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.dsl: reject name mismatch in `m.domains.<name>... |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.dsl: type check when adding to m.domains. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support. |
tree | commitdiff |
2020-02-04 |
whitequark | hdl.{ast,dsl}: allow whitespace in bit patterns. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.dsl: don't allow inheriting from Module. |
tree | commitdiff |
2020-01-31 |
whitequark | hdl.dsl: add missing case width check for Enum values. |
tree | commitdiff |
2020-01-31 |
whitequark | hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. |
tree | commitdiff |
2020-01-31 |
Jaro Habiger | build.dsl: allow strings to be used as connector numbers. |
tree | commitdiff |
2020-01-18 |
whitequark | hdl.ir: resolve hierarchy conflicts before creating... |
tree | commitdiff |
2020-01-17 |
whitequark | hdl.xfrm: transform drivers as well in DomainRenamer. |
tree | commitdiff |
2020-01-12 |
whitequark | Remove everything deprecated in nmigen 0.1. |
tree | commitdiff |
2020-01-11 |
Staf Verhaegen | Signal: allow to use integral Enum for reset value. |
tree | commitdiff |
2019-12-04 |
Marcin Kościelnicki | hdl.ast: Fix width for unary minus operator on signed... |
tree | commitdiff |
2019-11-28 |
whitequark | back.pysim: redesign the simulator. |
tree | commitdiff |
2019-11-26 |
whitequark | hdl.ir: for instance ports, prioritize defs over uses. |
tree | commitdiff |
2019-11-15 |
whitequark | build.plat: in Platform.add_file(), allow adding exact... |
tree | commitdiff |
2019-11-15 |
whitequark | test: add tests for build.plat.Platform.add_file. |
tree | commitdiff |
2019-11-07 |
whitequark | hdl.ir: lower domains before resolving hierarchy conflicts. |
tree | commitdiff |
2019-10-26 |
whitequark | test: use `#nmigen:` magic comment instead of monkey... |
tree | commitdiff |
2019-10-26 |
whitequark | hdl.ast: simplify {bit,word}_select with constant offset. |
tree | commitdiff |
2019-10-13 |
whitequark | {,_}tools→{,_}utils |
tree | commitdiff |
2019-10-13 |
whitequark | hdl.ir: allow ClockSignal and ResetSignal in ports. |
tree | commitdiff |
2019-10-13 |
whitequark | hdl.ir: cast instance port connections to Values. |
tree | commitdiff |
2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop. |
tree | commitdiff |
2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
tree | commitdiff |
2019-10-11 |
whitequark | Rename remaining `wrap` methods to `cast`. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor... |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate Signal.{range,enum}. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: add an explicit Shape class, included in prelude. |
tree | commitdiff |
2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: simplify enum handling. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: Value.{wrap→cast} |
tree | commitdiff |
2019-10-04 |
whitequark | hdl.ast: prohibit signed divisors. |
tree | commitdiff |
2019-10-03 |
whitequark | build.dsl: accept Pins(invert=True). |
tree | commitdiff |
2019-10-02 |
whitequark | hdl.ast: don't crash on Mux(<bool>, ...). |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.dsl: add a diagnostic for `m.d.submodules += ...`. |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.mem: remove WritePort(priority=) argument. |
tree | commitdiff |
2019-09-23 |
whitequark | lib.cdc: add diagnostic checks for synchronization... |
tree | commitdiff |
2019-09-23 |
whitequark | lib.cdc: MultiReg→FFSynchronizer. |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.ast: cast Mux() selector to bool if it is not a... |
tree | commitdiff |
2019-09-23 |
whitequark | lib.fifo: handle depth=0, elaborating to a dummy FIFO... |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.mem,lib.fifo: use keyword-only arguments for memory... |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.mem: simplify. NFC. |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.ast: make Signal(name=) a keyword-only argument. |
tree | commitdiff |
2019-09-23 |
whitequark | lib.fifo: change FIFOInterface() diagnostics to follow... |
tree | commitdiff |
2019-09-23 |
whitequark | lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest... |
tree | commitdiff |
2019-09-23 |
whitequark | lib.fifo: make simulation read() and write() functions... |
tree | commitdiff |
2019-09-22 |
whitequark | hdl.rec: fix using Enum subclass as shape if direction... |
tree | commitdiff |
2019-09-22 |
whitequark | hdl.rec: allow using Enum subclass as shape. |
tree | commitdiff |
2019-09-21 |
whitequark | build.res: simplify clock constraints. |
tree | commitdiff |
2019-09-20 |
whitequark | hdl.mem: use 1 as reset value for ReadPort.en. |
tree | commitdiff |
2019-09-20 |
whitequark | hdl.ast: rename `nbits` to `width`. |
tree | commitdiff |
2019-09-20 |
whitequark | test.test_lib_fifo: fix typo. |
tree | commitdiff |
2019-09-20 |
whitequark | back.pysim: fix simulation of Value.xor(). |
tree | commitdiff |
2019-09-16 |
whitequark | hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value... |
tree | commitdiff |
2019-09-14 |
whitequark | hdl.ast: add Value.matches(), accepting same language... |
tree | commitdiff |
2019-09-14 |
whitequark | hdl.dsl: improve error messages for Case(). |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.xor, mapping to $reduce_xor. |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
tree | commitdiff |
2019-09-13 |
whitequark | lib.fifo: adjust properties to have consistent naming. |
tree | commitdiff |
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