x86: split insn templates' CPU field
[binutils-gdb.git] / opcodes / i386-opc.tbl
2023-11-09 Jan Beulichx86: split insn templates' CPU field
2023-11-09 Jan Beulichx86: Cpu64 handling improvements
2023-10-31 Hu, Lin1Support Intel USER_MSR
2023-09-27 Jan Beulichx86: fold FMA VEX and EVEX templates
2023-09-27 Jan Beulichx86: fold VAES/VPCLMULQDQ VEX and EVEX templates
2023-09-27 Jan Beulichx86: fold certain VEX and EVEX templates
2023-09-14 Jan Beulichx86: Vxy naming correction
2023-09-14 Jan Beulichx86: support AVX10.1 vector size restrictions
2023-09-14 Jan Beulichx86: make AES/PCMULQDQ respectively prereqs of VAES...
2023-09-01 Jan Beulichx86: rename CpuPCLMUL
2023-09-01 Jan Beulichx86: drop Size64 from VMOVQ
2023-08-02 Sam JamesRevert "2.41 Release sources"
2023-08-02 Nick Clifton2.41 Release sources
2023-07-27 Hu, Lin1Support Intel PBNDKB
2023-07-27 Haochen JiangSupport Intel SM4
2023-07-27 Haochen JiangSupport Intel SM3
2023-07-27 Haochen JiangSupport Intel SHA512
2023-07-27 konglin1Support Intel AVX-VNNI-INT16
2023-07-04 Jan Beulichx86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQ
2023-07-04 Jan Beulichx86: optimize pre-AVX512 {,V}PCMPGT* with identical...
2023-07-04 Jan Beulichx86: optimize pre-AVX512 {,V}PCMPEQQ with identical...
2023-06-16 Jan Beulichx86: shrink Masking insn attribute to a single bit...
2023-05-23 Zhang, JunSupport Intel FRED LKGS
2023-05-23 liuhongtRevert "Support Intel FRED LKGS"
2023-05-23 Zhang, JunSupport Intel FRED LKGS
2023-04-07 Haochen JiangSupport Intel AMX-COMPLEX
2023-03-20 Jan Beulichx86: drop "shimm" special case template expansions
2023-03-20 Jan Beulichx86: VexVVVV is now merely a boolean
2023-03-20 Jan Beulichx86: re-work build_modrm_byte()'s register assignment
2023-02-24 Jan Beulichx86: MONITOR/MWAIT are not SSE3 insns
2023-02-24 Jan Beulichx86-64: don't permit LAHF/SAHF with "generic64"
2023-02-24 Jan Beulichx86: have insns acting on segment selector values allow...
2023-02-24 Jan Beulichx86: restrict insn templates accepting negative 8-bit...
2023-02-22 Jan Beulichx86-64: LAR and LSL don't need REX.W
2023-02-22 Jan Beulichx86: optimize BT{,C,R,S} $imm,%reg
2023-02-14 Jan Beulichx86: {LD,ST}TILECFG use an extension opcode
2023-02-13 Michael MatzPR30120: fix x87 fucomp misassembled
2023-02-10 Jan Beulichx86: drop use of VEX3SOURCES
2023-02-10 Jan Beulichx86: drop use of XOP2SOURCES
2023-02-10 Jan Beulichx86: limit use of XOP2SOURCES
2023-01-27 Jan Beulichx86: use ModR/M for FPU insns with operands
2023-01-01 Alan ModraUpdate year range in copyright notice of binutils files
2022-12-21 Jan Beulichx86: rename CheckRegSize to CheckOperandSize
2022-12-19 Jan Beulichx86: omit Cpu prefixes from opcode table
2022-12-16 Jan Beulichx86: change representation of extension opcode
2022-12-12 Jan Beulichx86: further re-work insn/suffix recognition to also...
2022-12-12 Jan Beulichx86: drop (now) stray IsString
2022-12-12 Jan Beulichx86: re-work insn/suffix recognition
2022-12-03 H.J. Lux86: Allow 16-bit register source for LAR and LSL
2022-12-02 Jan Beulichx86: also use D for XCHG and TEST
2022-12-01 Jan Beulichx86: drop No_ldSuf
2022-12-01 Jan Beulichx86/Intel: drop LONG_DOUBLE_MNEM_SUFFIX
2022-12-01 Jan Beulichx86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX
2022-11-30 Jan Beulichx86: clean up after removal of support for gcc <= 2.8.1
2022-11-30 Jan Beulichx86: drop FloatR
2022-11-24 Jan Beulichx86: widen applicability and use of CheckRegSize
2022-11-24 Jan Beulichx86: add missing CheckRegSize
2022-11-24 Jan Beulichx86: correct handling of LAR and LSL
2022-11-17 H.J. Luopcodes: Define NoSuf in i386-opc.tbl
2022-11-15 Tejas JoshiAdd AMD znver4 processor support
2022-11-14 Jan Beulichx86: fold special-operand insn attributes into a single...
2022-11-11 Jan Beulichx86: drop stray IsString from PadLock insns
2022-11-08 Kong LinglingSupport Intel RAO-INT
2022-11-04 konglin1Support Intel AVX-NE-CONVERT
2022-11-04 konglin1i386: Rename <xy> template.
2022-11-02 Jan Beulichx86: drop bogus Tbyte
2022-11-02 Hu, Lin1Support Intel MSRLIST
2022-11-02 Hu, Lin1Support Intel WRMSRNS
2022-11-02 Haochen JiangSupport Intel CMPccXADD
2022-11-02 Cui,LiliSupport Intel AVX-VNNI-INT8
2022-11-02 Hongyu WangSupport Intel AVX-IFMA
2022-10-31 Cui, LiliSupport Intel PREFETCHI
2022-10-21 Cui,LiliSupport Intel AMX-FP16
2022-10-20 Jan Beulichx86: re-work AVX-VNNI support
2022-09-30 Jan Beulichx86/Intel: restrict suffix derivation
2022-08-16 Jan Beulichx86: shorten certain template names
2022-08-16 Jan Beulichx86: template-ize certain vector conversion insns
2022-08-16 Jan Beulichx86: template-ize vector packed byte/word integer insns
2022-08-16 Jan Beulichx86: re-order AVX512 S/G templates
2022-08-16 Jan Beulichx86: template-ize vector packed dword/qword integer...
2022-08-16 Jan Beulichx86: template-ize packed/scalar vector floating point...
2022-08-16 Jan Beulichrevert "x86: Also pass -P to $(CPP) when processing...
2022-08-09 Jan Beulichx86-64: adjust MOVQ to/from SReg attributes
2022-08-09 Jan Beulichx86: adjust MOVSD attributes
2022-08-09 Jan Beulichx86: fold AVX VGATHERDPD / VPGATHERDQ
2022-08-09 Jan Beulichx86: allow use of broadcast with X/Y/Z-suffixed AVX512...
2022-08-09 Jan Beulichx86/Intel: split certain AVX512-FP16 VCVT*2PH templates
2022-08-03 Jan Beulichx86: properly mark i386-only insns
2022-08-03 Jan Beulichx86: also use D for MOVBE
2022-08-02 Jan Beulichx86: XOP shift insns don't really allow B suffix
2022-08-01 Jan Beulichx86: SKINIT with operand needs IgnoreSize
2022-07-29 Jan Beulichx86: drop stray NoRex64 from KeyLocker insns
2022-07-21 Jan Beulichx86: replace wrong attributes on VCVTDQ2PH{X,Y}
2022-07-21 Jan Beulichx86/Intel: correct AVX512F scatter insn element sizes
2022-07-18 Jan Beulichx86: correct VMOVSH attributes
2022-07-06 Jan Beulichx86: make D attribute usable for XOP and FMA4 insns
2022-07-04 Jan Beulichx86: fold Disp32S and Disp32
2022-06-29 Jan Beulichx86: drop stray NoRex64 from XBEGIN
2022-05-27 Jan Beulichx86: re-work AVX512 embedded rounding / SAE
2022-04-27 Jan Beulichx86: VFPCLASSSH is Evex.LLIG
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