bug 1034: invert ordering of lut indices to match xxeval
[openpower-isa.git] / openpower / isa / bitmanip.mdwn
2024-02-05 Luke Kenneth Casso... bug 1034: invert ordering of lut indices to match xxeval
2024-02-03 Luke Kenneth Casso... fix merge
2024-01-29 Luke Kenneth Casso... bug 1034: cut/paste error on crternlogi, 4*BT+32 should...
2024-01-27 Luke Kenneth Casso... bug 1034: yet again move crternlogi due to size of...
2024-01-27 Luke Kenneth Casso... bug 10344: had to move crfternlogi to TLI-Form
2024-01-25 Luke Kenneth Casso... bug 1034: add crbinlog and crternlogi, rename crbinlog...
2024-01-20 Luke Kenneth Casso... bug 1034: add crbinlog and binlog, unit test binlog...
2024-01-17 Luke Kenneth Casso... bug 1034: add crternlogi. involved adding a new CR...
2023-12-07 Luke Kenneth Casso... add first gather instruction pseudocode
2023-09-12 Jacob Lifshayremove grev, leaving unit tests for later use by grevlut
2023-05-27 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=1091
2023-04-18 Jacob Lifshayadd shaddw
2023-04-18 Jacob Lifshayspelling fix
2023-01-24 Dmitry Selyutinbitmanip.mdwn: add missing Rc static operand
2022-11-01 Dmitry Selyutinbitmanip.mdwn: avoid overflow for m variable
2022-11-01 Dmitry SelyutinRevert "Revert "https://bugs.libre-soc.org/show_bug...
2022-11-01 Dmitry SelyutinRevert "corrections to shadd/uw after reverting to...
2022-11-01 Luke Kenneth Casso... corrections to shadd/uw after reverting to switch
2022-11-01 Luke Kenneth Casso... Revert "https://bugs.libre-soc.org/show_bug.cgi?id...
2022-10-27 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=966#c4
2022-10-25 Luke Kenneth Casso... comments
2022-10-25 Luke Kenneth Casso... shadd pseudocode cleanup
2022-10-25 Dmitry Selyutinbitmanip.mdwn: support shadd/shadduw instructions
2022-08-30 Luke Kenneth Casso... correct the bitmanip pseudocode to remove spaces from...
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-14 Jacob Lifshayremove stray newline
2022-01-14 Jacob Lifshayadd grev[w][i][.] pseudo-code
2021-12-11 Luke Kenneth Casso... remove ROTL64(1, idx), just use TLI[7-idx] it is shorte...
2021-12-11 Luke Kenneth Casso... use concat in ternlogi to reduce code size
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Jacob Lifshayadd initial ternlogi pseudo-code