latches are always set to zero
[yosys.git] / passes / sat / sim.cc
2022-04-22 Miodrag Milanoviclatches are always set to zero
2022-04-22 Miodrag MilanovicIf not multiclock, output only on clock edges
2022-04-22 Miodrag MilanovicSet init state for all wires from FST and set past
2022-04-22 Miodrag MilanovicFix multiclock for btor2 witness
2022-04-18 Miodrag MilanovićMerge pull request #3280 from YosysHQ/micko/fix_readaiw
2022-04-15 Miodrag MilanovicFix reading aiw from other solvers
2022-04-04 Miodrag MilanovićMerge pull request #3265 from YosysHQ/micko/sim_improve...
2022-04-02 Miodrag Milanovicpast_ad initial value setting
2022-04-02 Miodrag MilanovicsetInitState can be only one altering values
2022-04-02 Miodrag MilanovicSet past_d value for init state
2022-03-31 Miodrag MilanovićMerge pull request #3256 from YosysHQ/micko/aiw_multiclock
2022-03-31 Miodrag Milanovic Support memories in aiw and multiclock
2022-03-28 LoftyMerge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-22 Miodrag MilanovicProper SigBit forming in sim
2022-03-22 Miodrag MilanovicProper SigBit forming in sim
2022-03-18 Miodrag MilanovicMore verbose warnings
2022-03-17 Miodrag MilanovićMerge pull request #3236 from YosysHQ/micko/tb_initial
2022-03-16 Miodrag MilanovicRecognize registers and set initial state for them...
2022-03-16 Miodrag MilanovicUpdate sim help message.
2022-03-14 Miodrag MilanovićMerge pull request #3232 from YosysHQ/micko/fst2tb
2022-03-14 Miodrag MilanovicAdded fst2tb pass for generating testbench
2022-03-14 Claire XenMerge pull request #3213 from antonblanchard/abc-typo
2022-03-11 Miodrag MilanovićMerge pull request #3229 from YosysHQ/micko/sim_date
2022-03-11 Miodrag MilanovićMerge pull request #3222 from zachjs/prune-linux-ci
2022-03-11 Miodrag MilanovićMerge pull request #3228 from YosysHQ/micko/disable_tests
2022-03-11 Claire Xenia WolfAdd "sim -q" option
2022-03-11 Miodrag MilanovicAdd date parameter to enable full date/time and version...
2022-03-11 Claire Xenia WolfSmall fix in "sim" help message
2022-03-11 Miodrag MilanovićMerge pull request #3226 from YosysHQ/micko/btor2witness
2022-03-11 Miodrag MilanovicFstData already do conversion to VCD
2022-03-11 Miodrag MilanovicSupport cell name in btor witness file
2022-03-11 Miodrag MilanovicProper write of memory data
2022-03-09 Miodrag MilanovicStart work on memory init
2022-03-09 Miodrag MilanovicFixes and error check
2022-03-07 Miodrag Milanoviccleanup
2022-03-07 Miodrag MilanovicError checks for aiger witness
2022-03-07 Miodrag Milanovicbtor2 witness co-simulation
2022-03-07 Miodrag MilanovićMerge pull request #3210 from rqou/json-signed
2022-03-04 Miodrag MilanovićMerge pull request #3186 from nakengelhardt/smtbmc_sby_...
2022-03-04 Miodrag MilanovićMerge pull request #3206 from YosysHQ/micko/quote_remove
2022-03-04 Miodrag MilanovićMerge pull request #3207 from nakengelhardt/json_escape...
2022-03-04 Miodrag MilanovićMerge pull request #3219 from YosysHQ/micko/quick_vcd
2022-03-04 Miodrag MilanovićMerge pull request #3220 from YosysHQ/claire/simstuff
2022-03-02 Miodrag MilanovicAdd option to ignore X only signals in output
2022-03-02 Miodrag MilanovicWrite simulation files after simulation is performed
2022-03-02 Claire XenMerge pull request #3224 from YosysHQ/micko/refactor
2022-03-02 Miodrag MilanovicCleanup
2022-02-28 Miodrag MilanovicRefactor sim output writers
2022-02-28 Miodrag MilanovicQuick fix
2022-02-28 Claire Xenia WolfAdd writing of aiw files to "sim" command
2022-02-28 Claire Xenia WolfHotfix in AIGER witness reader state machine
2022-02-28 Miodrag MilanovicVCD reader support by using external tool
2022-02-28 Miodrag MilanovićMerge pull request #3216 from YosysHQ/claire/simstuff
2022-02-27 Miodrag MilanovicSupport extended aiw format
2022-02-25 Miodrag MilanovicFix for last clock edge data
2022-02-25 Claire Xenia WolfExperimental sim changes
2022-02-22 Claire XenMerge pull request #3211 from YosysHQ/micko/witness
2022-02-22 Claire XenMerge pull request #3197 from YosysHQ/claire/smtbmcfix
2022-02-21 Miodrag MilanovićMerge pull request #3203 from YosysHQ/micko/sim_ff
2022-02-21 Miodrag MilanovicFix handling of ce_over_srst
2022-02-18 Claire Xenia WolfFix cycle 0 in aiger witness co-simulation
2022-02-18 Miodrag MilanovicAdded AIGER witness file co simulation
2022-02-18 Miodrag Milanovicsimplify logic of handling flip-flops and latches
2022-02-17 Miodrag MilanovicReview cleanup
2022-02-16 Miodrag MilanovicAdd support for various ff/latch cells simulation
2022-02-11 Miodrag MilanovićMerge pull request #3164 from zachjs/fix-ast-warn
2022-02-11 Claire XenMerge branch 'master' into clk2ff-better-names
2022-02-11 Claire XenMerge pull request #2019 from boqwxp/glift
2022-02-07 Miodrag MilanovićMerge pull request #3185 from YosysHQ/micko/co_sim
2022-02-04 Miodrag MilanovicError detection for co-simulation
2022-02-04 Miodrag Milanovicbug fix and cleanups
2022-02-02 Miodrag Milanovicrespect hide_internal flag
2022-02-02 Miodrag Milanovicunify cycles counting and cleanup
2022-02-02 Miodrag Milanovicadded stimulus mode and param check
2022-01-31 Miodrag Milanovicerror when no signal found
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag MilanovicCompare bits when not all are defined
2022-01-31 Miodrag MilanovicCleanup
2022-01-31 Miodrag Milanovicmessage update
2022-01-31 Miodrag MilanovicDisplay simulation time data
2022-01-31 Miodrag MilanovicUse edges when explicit
2022-01-31 Miodrag MilanovicUpdating initial state and checks
2022-01-31 Miodrag MilanovicFix scope
2022-01-28 Marcelina KościelnickaAdd $bmux and $demux cells.
2022-01-28 Miodrag Milanoviccheck if stop before start
2022-01-28 Miodrag Milanovicset initial state, only flip-flops
2022-01-28 Miodrag Milanovicignore not found private signals
2022-01-28 Miodrag Milanovicrecursive check
2022-01-28 Miodrag MilanovicDo actual compare
2022-01-28 Miodrag MilanovicAdd more options and time handling
2022-01-26 Miodrag MilanovicDisplay values of outputs
2022-01-26 Miodrag MilanovicCheck if stimulated
2022-01-26 Miodrag MilanovicRead fst and use data to set inputs
2022-01-26 Miodrag MilanovicAdd ability to write to FST file
2021-07-28 Marcelina Kościelnickamemory: Introduce $meminit_v2 cell, with EN input.
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-07 Claire Xenia WolfFixing old e-mail addresses and deadnames
2021-05-25 Marcelina Kościelnickasim: Add wide port support.
2021-05-22 Marcelina Kościelnickakernel/rtlil: Extract some helpers for checking memory...
2021-03-11 whitequarkMerge pull request #2642 from whitequark/cxxrtl-noproc...
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