Turned the add_1 verilog state into nmigen
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
2019-02-14 Aleksandar KostovicTurned the add_1 verilog state into nmigen
2019-02-14 Luke Kenneth Casso... whoops accidentally indented too far
2019-02-14 Luke Kenneth Casso... add code comments
2019-02-14 Luke Kenneth Casso... reformat / indent add_0 stage
2019-02-14 Aleksandar KostovicTurned the add_0 verilog state into nmigen
2019-02-14 Luke Kenneth Casso... add zero and denormalised checks
2019-02-14 Luke Kenneth Casso... add special case, b when a is zero
2019-02-14 Luke Kenneth Casso... add b inf special case
2019-02-14 Luke Kenneth Casso... cleanup and comments
2019-02-14 Luke Kenneth Casso... add inf special case
2019-02-14 Luke Kenneth Casso... whitespace (indent)
2019-02-14 Luke Kenneth Casso... add first of special_cases
2019-02-14 Luke Kenneth Casso... invert Cat order, use 3 zeros (3 bits)
2019-02-14 Luke Kenneth Casso... spelling correction
2019-02-14 Luke Kenneth Casso... corrected syntax for unpack block
2019-02-13 Aleksandar KostovicReplicated unpack part of always block into nmigen
2019-02-13 Luke Kenneth Casso... add experiment