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fix tied input-output equivalence checking
[bigint-presentation-code.git]
/
src
/
bigint_presentation_code
/
compiler_ir2.py
2022-11-03
Jacob Lifshay
fix tied input-output equivalence checking
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2022-11-03
Jacob Lifshay
working on code
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2022-11-02
Jacob Lifshay
working on code
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2022-11-01
Jacob Lifshay
working on refactoring register allocator to use new ir
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2022-11-01
Jacob Lifshay
validate that tied outputs are equivalent to their...
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2022-11-01
Jacob Lifshay
add pre_ra_insert_copies
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2022-11-01
Jacob Lifshay
change Op/Ty/SSAVal reprs to be easier to read
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2022-10-31
Jacob Lifshay
pre-ra simulation works with new ir
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2022-10-30
Jacob Lifshay
implement more of new compiler ir
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2022-10-29
Jacob Lifshay
working on new ir
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2022-10-28
Jacob Lifshay
working on rewriting compiler ir to fix reg alloc issues
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2022-10-27
Jacob Lifshay
WIP rewriting compiler IR so regalloc works correctly
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