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split step counter into clock and substep
[nmigen-gf.git]
/
src
/
nmigen_gf
/
hdl
/
cldivrem.py
2022-05-06
Jacob Lifshay
split step counter into clock and substep
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2022-05-05
Jacob Lifshay
remove now-unused EqualLeadingZeroCount
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2022-05-05
Jacob Lifshay
switch to better CLDivRem algorithm
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2022-05-05
Jacob Lifshay
shrink signal widths
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2022-05-05
Jacob Lifshay
add cldivrem_shifting as a more efficient algorithm
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2022-05-04
Jacob Lifshay
implement CLDivRemFSMStage
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2022-04-08
Jacob Lifshay
clean up EqualLeadingZeroCount.elaborate
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2022-04-08
Luke Kenneth Casso...
move NOT into carrysum so that variable name
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2022-04-07
Luke Kenneth Casso...
remove addend1 and addend2 just add bothones and different.
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2022-04-07
Luke Kenneth Casso...
code-comments
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2022-04-07
Luke Kenneth Casso...
doh
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2022-04-07
Luke Kenneth Casso...
simplify code by removing for-loop and commenting why...
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2022-04-07
Jacob Lifshay
remove unused imports
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2022-04-07
Jacob Lifshay
switch EqualLeadingZeroCount to use bitwise logic rathe...
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2022-04-07
Jacob Lifshay
change reference algorithm to be more amenable to bitwi...
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2022-04-05
Jacob Lifshay
working on adding CLDivRem
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