bug 1034: add crbinlog and crternlogi, rename crbinlog to crfbinlog
[openpower-isa.git] / src / openpower / test / bitmanip / bitmanip_cases.py
2024-01-25 Luke Kenneth Casso... bug 1034: add crbinlog and crternlogi, rename crbinlog...
2024-01-20 Luke Kenneth Casso... bug 1034: add crbinlog unit test, fix binlog test,...
2024-01-20 Luke Kenneth Casso... bug 1034: add crbinlog and binlog, unit test binlog...
2024-01-17 Luke Kenneth Casso... bug 1034: add crternlogi. involved adding a new CR...
2023-12-07 Luke Kenneth Casso... add gbbd (bmatflip) test case - just the one for now
2023-09-12 Jacob Lifshayremove grev, leaving unit tests for later use by grevlut
2023-07-22 Luke Kenneth Casso... shortened variable names,
2023-07-22 Jacob Lifshayadd SVP64 test for byte reverse insns
2023-07-20 Jacob Lifshayadd byte reverse instructions from PowerISA v3.1B
2023-06-02 Dmitry Selyutinpysvp64asm: integrate into insndb
2022-08-13 Luke Kenneth Casso... invalidate grev cases, replaced by grevlut
2022-05-03 Jacob Lifshayadd Rc to ternlogi
2022-01-18 Jacob Lifshaygrev[w][i][.] pseudo-code works
2022-01-06 Jacob Lifshayadd stand-alone simulator bitmanip test
2021-12-10 Jacob Lifshayadd ternlogi to SVP64Asm
2021-12-10 Jacob Lifshaychange ternlogi to not have Rc field
2021-12-09 Jacob Lifshaymake ternlogi tests run
2021-12-09 Jacob Lifshayrename ternaryi to ternlogi
2021-11-17 Jacob Lifshayadd bitmanip_cases.py