format code
[soc.git] / src / soc / simple / test / test_runner.py
2021-12-09 Jacob Lifshayformat code
2021-12-05 Luke Kenneth Casso... correct import of wg_get function
2021-11-24 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-24 Luke Kenneth Casso... when allow_overlap enabled do a manual wait until all...
2021-11-22 Luke Kenneth Casso... whoops accidentally committed commented-out test for...
2021-11-21 Luke Kenneth Casso... complex. TestRunner now does not work properly unless...
2021-11-19 Luke Kenneth Casso... debug and cleanup
2021-11-19 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-18 Luke Kenneth Casso... experiment allowing overlap (activated with --allow...
2021-11-18 Luke Kenneth Casso... remove unneeded import
2021-11-17 Luke Kenneth Casso... add option to test_issuer.py to allow for overlapping...
2021-10-08 klehmancomments for test_runner pr
2021-10-08 Luke Kenneth Casso... move TestRunner to openpower-isa now that it is part...
2021-10-08 klehmanadd a state list for method calling
2021-10-08 Luke Kenneth Casso... found accidental commenting-out of memory setup in...
2021-10-08 Luke Kenneth Casso... move debug printout to see whats going on for ldst
2021-10-08 Luke Kenneth Casso... comments
2021-10-08 Luke Kenneth Casso... Revert "move coresync clock synchronisation into HDLRunner"
2021-10-08 Luke Kenneth Casso... call StateRunner constructor, to add to StateRunner...
2021-10-08 Luke Kenneth Casso... more TODO comments
2021-10-08 Luke Kenneth Casso... move coresync clock synchronisation into HDLRunner
2021-10-08 Luke Kenneth Casso... whoops missed one function which should be a yield...
2021-10-08 Luke Kenneth Casso... use yield from on StateRunners
2021-10-08 Luke Kenneth Casso... add comments, remove unneeded code
2021-10-08 Luke Kenneth Casso... move pc_i and svstate_i to HDLRunner
2021-10-08 klehmanadd end_test, minor cleanup, added hdlrun.cleanup(...
2021-10-08 klehmanmoved pc_i and sv_state to constructor, remove hdl_stat...
2021-10-08 klehmanchange over run_hdl_state to TestRunner class
2021-10-08 Luke Kenneth Casso... add dummy call to simrun and end_test()
2021-10-08 Luke Kenneth Casso... code-comments and dummy functions
2021-10-08 Luke Kenneth Casso... move contents of run_sim_state into SimRunner run_test...
2021-10-08 Luke Kenneth Casso... add a SimRunner prepare_for_test and run_test function
2021-10-07 klehmancomments for test_runner
2021-10-01 Luke Kenneth Casso... move TestRunner to openpower-isa now that it is part...
2021-09-26 klehmanadd a state list for method calling
2021-09-25 Luke Kenneth Casso... found accidental commenting-out of memory setup in...
2021-09-25 Luke Kenneth Casso... move debug printout to see whats going on for ldst
2021-09-25 Luke Kenneth Casso... comments
2021-09-25 Luke Kenneth Casso... Revert "move coresync clock synchronisation into HDLRunner"
2021-09-25 Luke Kenneth Casso... call StateRunner constructor, to add to StateRunner...
2021-09-25 Luke Kenneth Casso... more TODO comments
2021-09-25 Luke Kenneth Casso... move coresync clock synchronisation into HDLRunner
2021-09-25 Luke Kenneth Casso... whoops missed one function which should be a yield...
2021-09-25 Luke Kenneth Casso... use yield from on StateRunners
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-25 Luke Kenneth Casso... add comments, remove unneeded code
2021-09-25 Luke Kenneth Casso... move pc_i and svstate_i to HDLRunner
2021-09-25 klehmanadd end_test, minor cleanup, added hdlrun.cleanup(...
2021-09-25 klehmanmoved pc_i and sv_state to constructor, remove hdl_stat...
2021-09-25 klehmanchange over run_hdl_state to TestRunner class
2021-09-25 Luke Kenneth Casso... add dummy call to simrun and end_test()
2021-09-25 Luke Kenneth Casso... code-comments and dummy functions
2021-09-25 Luke Kenneth Casso... move contents of run_sim_state into SimRunner run_test...
2021-09-25 Luke Kenneth Casso... add a SimRunner prepare_for_test and run_test function
2021-09-25 klehmanstart of HDLRunner
2021-09-24 Luke Kenneth Casso... create initial SimRunner
2021-09-23 Luke Kenneth Casso... move pc_i and svstate_i inside if self.run_hdl
2021-09-23 Luke Kenneth Casso... more comments
2021-09-23 Luke Kenneth Casso... add in a stack of comments for identifying match-points...
2021-09-23 Luke Kenneth Casso... add option to run ISACaller Sim (or not)
2021-09-23 Luke Kenneth Casso... add a new run_hdl parameter to TestRunner
2021-09-22 Luke Kenneth Casso... completely borked python segfault, workaround to copy...
2021-09-22 Luke Kenneth Casso... add test of expected results against last sim state
2021-09-22 Luke Kenneth Casso... whoops broken run_sim_state function
2021-09-22 Luke Kenneth Casso... split out HDL from Simulator into separate functions
2021-09-22 Luke Kenneth Casso... split out HDL test from Simulator test,
2021-09-22 Luke Kenneth Casso... alter setup_tst_memory to take a test.mem rather than...
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 klehmanchanged test_runner to use state mem compare
2021-09-17 Luke Kenneth Casso... update comments
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-16 Cesar StraussAdjust PortInterface traces according to MMU option
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-07-15 Luke Kenneth Casso... update TestRunner, SVSTATE is now a class that inherits...
2021-07-14 Luke Kenneth Casso... update SVSTATE to 64 bit length (fortunately very easy)
2021-07-12 Luke Kenneth Casso... use standard create_pdecode in TestRunner
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-07-10 Cesar StraussShow some usage of PortInterface in action
2021-05-22 Cesar StraussMove the reset code outside of the sub-test
2021-05-07 Luke Kenneth Casso... how we managed to get this far without noticing that...
2021-05-01 Luke Kenneth Casso... send a DMI RESET at the end of the test.
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... add basic test_issuer_mmu.py
2021-04-30 Luke Kenneth Casso... add option to use new mmu_cache_wb ConfigMemoryPortInte...
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-03 Cesar StraussAllow the Simulator to handle back-to-back signaling...
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Luke Kenneth Casso... use port name for INT regfile to match up with test_run...
2021-03-30 Cesar StraussMemory port seems to have been renamed
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size
2021-03-28 Luke Kenneth Casso... reduce number of regfile ports
2021-03-22 Cesar StraussAdd traces for the new FSM and integer predicate decoding
2021-03-09 Cesar StraussAdd some extra debug traces to the GTKWave document
2021-03-09 Cesar StraussCreate a new signal for the Simulator to wait on
2021-03-08 Luke Kenneth Casso... add option in TestRunner to disable svp64 via commandli...
2021-03-03 Luke Kenneth Casso... set SVSTATE in TestRunner using new TestIssuer.svstate_i
2021-03-03 Luke Kenneth Casso... add svstate_i to TestIssuer which mirrors pc_i
2021-02-27 Cesar StraussAdd traces for the new FSM
2021-02-24 Tobias Platentest_runner.py: add needed imports
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