Merge pull request #3310 from robinsonb5-PRs/master
[yosys.git] / tests / asicworld /
2020-01-29 Claire WolfMerge branch 'vector_fix' of https://github.com/Kmanfi...
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-19 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-03-14 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-03-09 Clifford WolfMerge pull request #859 from smunaut/ice40_braminit
2019-03-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-01 Clifford WolfMerge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
2019-02-28 Clifford WolfMerge pull request #794 from daveshah1/ecp5improve
2019-02-28 Clifford WolfMerge pull request #827 from ucb-bar/firrtlfixes
2019-02-26 Jim LawsonFix FIRRTL to Verilog process instance subfield assignment.
2019-02-26 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-02-24 Clifford WolfMerge pull request #812 from ucb-bar/arrayhierarchyfixes
2019-02-22 Clifford WolfMerge pull request #740 from daveshah1/improve_dress
2019-02-19 Eddie HungMerge branch 'master' into xaig
2019-02-19 Eddie HungMerge branch 'master' into read_aiger
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into dff_init
2019-02-17 Eddie HungMerge https://github.com/YosysHQ/yosys into read_aiger
2019-02-17 Clifford WolfMerge branch 'master' of github.com:YosysHQ/yosys into...
2019-02-17 Clifford WolfMerge pull request #811 from ucb-bar/firrtlfixes
2019-02-15 Jim LawsonAppend (instead of over-writing) EXTRA_FLAGS
2019-02-15 Jim LawsonUpdate cells supported for verilog to FIRRTL conversion.
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-01-27 Clifford WolfMerge pull request #798 from mmicko/master
2019-01-27 Clifford WolfMerge pull request #800 from whitequark/write_verilog_t...
2019-01-27 Clifford WolfMerge branch 'whitequark-write_verilog_keyword'
2019-01-27 Clifford WolfRemove asicworld tests for (unsupported) switch-level...
2016-09-23 Clifford WolfMerge branch 'master' of https://github.com/brouhaha...
2016-09-22 Eric SmithAdd optional SEED=n command line option to Makefile...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-05-20 Clifford WolfSome fixes in tests/asicworld/*_tb.v
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 Clifford WolfFixed CRLF line endings
2015-08-13 Clifford WolfSome ASCII encoding fixes (comments and docs) by Larry...
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-12 Clifford WolfSome test related fixes
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-30 Clifford WolfAdded autotest -e (do not use -noexpr on write_verilog)
2014-07-30 Clifford WolfAdded "make -j{N}" support to "make test"
2014-07-16 Clifford WolfAdded note to "make test": use git checkout of iverilog
2014-06-15 Clifford WolfAdded tests/realmath to "make test"
2013-05-24 Clifford WolfFixed undef behavior in tests/asicworld/code_verilog_tu...
2013-01-05 Clifford Wolfadded more .gitignore files (make test)
2013-01-05 Clifford Wolfinitial import