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begin working on linux verilator simulation
[microwatt.git]
/
wishbone_bram_wrapper.vhdl
2022-04-12
Tobias Platen
revert changes in wishbone_bram_wrapper.vhdl
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2022-04-03
Tobias Platen
ram addr calculation ram_addr
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2022-04-03
Tobias Platen
backport wishbone_bram_wrapper changes
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2022-03-27
Tobias Platen
more work on verilator backport
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2022-03-22
Tobias Platen
Merge remote-tracking branch 'to-be-merged/merge-3d...
merge-3d-game
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2022-03-18
Michael Neuling
Merge pull request #360 from antonblanchard/log2ceil...
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2022-03-17
Anton Blanchard
wishbone_bram_wrapper ram_addr_bits is 1 bit off
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2021-09-24
Paul Mackerras
Merge pull request #330 from antonblanchard/orange...
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2021-09-24
Anton Blanchard
Merge pull request #331 from ozbenh/misc
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2021-09-24
Anton Blanchard
Merge pull request #329 from paulusmack/wb-fix
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2021-09-15
Paul Mackerras
Make wishbone addresses be in units of doublewords...
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2021-08-16
Michael Neuling
Merge pull request #318 from paulusmack/pmu
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2021-08-14
Paul Mackerras
Merge pull request #316 from antonblanchard/verilator-fix
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2021-08-13
Anton Blanchard
Rename 'do' signal to avoid verilator System Verilog...
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2020-01-21
Anton Blanchard
Merge pull request #134 from paulusmack/master
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2020-01-19
Anton Blanchard
Merge pull request #139 from antonblanchard/reduce-mem
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2020-01-19
Anton Blanchard
Add log2ceil and use it in bram code
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2019-11-15
Anton Blanchard
Merge pull request #118 from antonblanchard/bus-pipeline
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2019-10-30
Benjamin Herrenschmidt
ram: Ack stores early
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2019-10-30
Benjamin Herrenschmidt
ram: Rework main RAM interface
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