begin working on linux verilator simulation
[microwatt.git] / wishbone_bram_wrapper.vhdl
2022-04-12 Tobias Platenrevert changes in wishbone_bram_wrapper.vhdl
2022-04-03 Tobias Platenram addr calculation ram_addr
2022-04-03 Tobias Platenbackport wishbone_bram_wrapper changes
2022-03-27 Tobias Platenmore work on verilator backport
2022-03-22 Tobias PlatenMerge remote-tracking branch 'to-be-merged/merge-3d... merge-3d-game
2022-03-18 Michael NeulingMerge pull request #360 from antonblanchard/log2ceil...
2022-03-17 Anton Blanchardwishbone_bram_wrapper ram_addr_bits is 1 bit off
2021-09-24 Paul MackerrasMerge pull request #330 from antonblanchard/orange...
2021-09-24 Anton BlanchardMerge pull request #331 from ozbenh/misc
2021-09-24 Anton BlanchardMerge pull request #329 from paulusmack/wb-fix
2021-09-15 Paul MackerrasMake wishbone addresses be in units of doublewords...
2021-08-16 Michael NeulingMerge pull request #318 from paulusmack/pmu
2021-08-14 Paul MackerrasMerge pull request #316 from antonblanchard/verilator-fix
2021-08-13 Anton BlanchardRename 'do' signal to avoid verilator System Verilog...
2020-01-21 Anton BlanchardMerge pull request #134 from paulusmack/master
2020-01-19 Anton BlanchardMerge pull request #139 from antonblanchard/reduce-mem
2020-01-19 Anton BlanchardAdd log2ceil and use it in bram code
2019-11-15 Anton BlanchardMerge pull request #118 from antonblanchard/bus-pipeline
2019-10-30 Benjamin Herrenschmidtram: Ack stores early
2019-10-30 Benjamin Herrenschmidtram: Rework main RAM interface