yosys.git
2 years agoMerge pull request #3297 from jix/sva_nested_clk_else
Jannis Harder [Mon, 9 May 2022 14:07:39 +0000 (16:07 +0200)]
Merge pull request #3297 from jix/sva_nested_clk_else

verific: Fix conditions of SVAs with explicit clocks within procedures

2 years agoNext dev cycle
Miodrag Milanovic [Mon, 9 May 2022 08:12:32 +0000 (10:12 +0200)]
Next dev cycle

2 years agoRelease version 0.17 yosys-0.17
Miodrag Milanovic [Mon, 9 May 2022 08:11:04 +0000 (10:11 +0200)]
Release version 0.17

2 years agoUpdate CHANGELOG
Miodrag Milanovic [Mon, 9 May 2022 08:06:15 +0000 (10:06 +0200)]
Update CHANGELOG

2 years agoUpdate manual
Miodrag Milanovic [Mon, 9 May 2022 07:53:01 +0000 (09:53 +0200)]
Update manual

2 years agoMerge pull request #3299 from YosysHQ/mmicko/sim_memory
Miodrag Milanović [Mon, 9 May 2022 07:28:09 +0000 (09:28 +0200)]
Merge pull request #3299 from YosysHQ/mmicko/sim_memory

sim pass: support for memories

2 years agoFix running sva tests
Miodrag Milanovic [Mon, 9 May 2022 07:01:57 +0000 (09:01 +0200)]
Fix running sva tests

2 years agoBump version
github-actions[bot] [Sun, 8 May 2022 00:16:45 +0000 (00:16 +0000)]
Bump version

2 years agoopt_mem: Remove constant-value bit lanes.
Marcelina Kościelnicka [Fri, 6 May 2022 21:29:16 +0000 (23:29 +0200)]
opt_mem: Remove constant-value bit lanes.

2 years agoBump version
github-actions[bot] [Sat, 7 May 2022 00:15:38 +0000 (00:15 +0000)]
Bump version

2 years agoinclude latest abc changes
Miodrag Milanovic [Fri, 6 May 2022 13:52:24 +0000 (15:52 +0200)]
include latest abc changes

2 years agoinclude latest abc changes
Miodrag Milanovic [Fri, 6 May 2022 13:42:39 +0000 (15:42 +0200)]
include latest abc changes

2 years agoMerge pull request #3300 from imhcyx/master
Miodrag Milanović [Fri, 6 May 2022 07:17:59 +0000 (09:17 +0200)]
Merge pull request #3300 from imhcyx/master

memory_share: fix wrong argidx in extra_args

2 years agoInclude abc change to fix FreeBSD build
Miodrag Milanovic [Fri, 6 May 2022 06:08:06 +0000 (08:08 +0200)]
Include abc change to fix FreeBSD build

2 years agoHandle possible non-memory indexed data
Miodrag Milanovic [Fri, 6 May 2022 06:05:23 +0000 (08:05 +0200)]
Handle possible non-memory indexed data

2 years agomemory_share: fix wrong argidx in extra_args
imhcyx [Thu, 5 May 2022 08:58:39 +0000 (16:58 +0800)]
memory_share: fix wrong argidx in extra_args

2 years agoBump version
github-actions[bot] [Thu, 5 May 2022 00:15:34 +0000 (00:15 +0000)]
Bump version

2 years agoabc: Use dict/pool instead of std::map/std::set
Marcelina Kościelnicka [Wed, 4 May 2022 18:43:59 +0000 (20:43 +0200)]
abc: Use dict/pool instead of std::map/std::set

2 years agomap memory location to wire value, if memory is converted to FFs
Miodrag Milanovic [Wed, 4 May 2022 11:08:16 +0000 (13:08 +0200)]
map memory location to wire value, if memory is converted to FFs

2 years agofix crash when no fst input
Miodrag Milanovic [Wed, 4 May 2022 09:21:39 +0000 (11:21 +0200)]
fix crash when no fst input

2 years agoStart restoring memory state from VCD/FST
Miodrag Milanovic [Wed, 4 May 2022 08:41:04 +0000 (10:41 +0200)]
Start restoring memory state from VCD/FST

2 years agoAdd propagated clock signals into btor info file
Claire Xenia Wolf [Wed, 4 May 2022 06:10:18 +0000 (08:10 +0200)]
Add propagated clock signals into btor info file

2 years agoverific: Fix conditions of SVAs with explicit clocks within procedures
Jannis Harder [Tue, 3 May 2022 11:22:18 +0000 (13:22 +0200)]
verific: Fix conditions of SVAs with explicit clocks within procedures

For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.

2 years agoBump version
github-actions[bot] [Tue, 3 May 2022 00:16:24 +0000 (00:16 +0000)]
Bump version

2 years agoAIM file could have gaps in or between inputs and inits
Miodrag Milanovic [Mon, 2 May 2022 09:18:30 +0000 (11:18 +0200)]
AIM file could have gaps in or between inputs and inits

2 years agoBump version
github-actions[bot] [Sat, 30 Apr 2022 00:18:55 +0000 (00:18 +0000)]
Bump version

2 years agoMerge pull request #3294 from YosysHQ/micko/verific_merge_past_ff
Miodrag Milanović [Fri, 29 Apr 2022 12:35:46 +0000 (14:35 +0200)]
Merge pull request #3294 from YosysHQ/micko/verific_merge_past_ff

Ignore merging past ffs that we are not properly merging

2 years agoIgnore merging past ffs that we are not properly merging
Miodrag Milanovic [Fri, 29 Apr 2022 12:35:02 +0000 (14:35 +0200)]
Ignore merging past ffs that we are not properly merging

2 years agoBump version
github-actions[bot] [Tue, 26 Apr 2022 00:18:47 +0000 (00:18 +0000)]
Bump version

2 years agoAdd missing parameters for ecp5
Rick Luiken [Fri, 8 Apr 2022 12:41:48 +0000 (14:41 +0200)]
Add missing parameters for ecp5

2 years agoMerge pull request #3287 from jix/smt2-conditional-store
Jannis Harder [Mon, 25 Apr 2022 14:23:21 +0000 (16:23 +0200)]
Merge pull request #3287 from jix/smt2-conditional-store

smt2: Make write port array stores conditional on nonzero write mask

2 years agoMerge pull request #3257 from jix/tribuf-formal
Jannis Harder [Mon, 25 Apr 2022 14:23:06 +0000 (16:23 +0200)]
Merge pull request #3257 from jix/tribuf-formal

tribuf: `-formal` option: convert all to logic and detect conflicts

2 years agoMerge pull request #3290 from mpasternacki/bugfix/freebsd-build
Miodrag Milanović [Mon, 25 Apr 2022 08:16:50 +0000 (10:16 +0200)]
Merge pull request #3290 from mpasternacki/bugfix/freebsd-build

Fix build on FreeBSD, which has no alloca.h

2 years agoMerge pull request #3289 from YosysHQ/micko/sim_improve
Miodrag Milanović [Mon, 25 Apr 2022 08:16:25 +0000 (10:16 +0200)]
Merge pull request #3289 from YosysHQ/micko/sim_improve

Simulation improvements

2 years agoFix build on FreeBSD, which has no alloca.h
Maciej Pasternacki [Sun, 24 Apr 2022 17:35:50 +0000 (19:35 +0200)]
Fix build on FreeBSD, which has no alloca.h

2 years agoMatch $anyseq input if connected to public wire
Miodrag Milanovic [Fri, 22 Apr 2022 15:20:17 +0000 (17:20 +0200)]
Match $anyseq input if connected to public wire

2 years agoTreat $anyseq as input from FST
Miodrag Milanovic [Fri, 22 Apr 2022 14:23:39 +0000 (16:23 +0200)]
Treat $anyseq as input from FST

2 years agoIgnore change on last edge
Miodrag Milanovic [Fri, 22 Apr 2022 13:24:02 +0000 (15:24 +0200)]
Ignore change on last edge

2 years agoLast sample from input does not represent change
Miodrag Milanovic [Fri, 22 Apr 2022 11:46:11 +0000 (13:46 +0200)]
Last sample from input does not represent change

2 years agolatches are always set to zero
Miodrag Milanovic [Fri, 22 Apr 2022 10:04:05 +0000 (12:04 +0200)]
latches are always set to zero

2 years agoIf not multiclock, output only on clock edges
Miodrag Milanovic [Fri, 22 Apr 2022 10:03:39 +0000 (12:03 +0200)]
If not multiclock, output only on clock edges

2 years agoSet init state for all wires from FST and set past
Miodrag Milanovic [Fri, 22 Apr 2022 09:57:39 +0000 (11:57 +0200)]
Set init state for all wires from FST and set past

2 years agoFix multiclock for btor2 witness
Miodrag Milanovic [Fri, 22 Apr 2022 09:53:41 +0000 (11:53 +0200)]
Fix multiclock for btor2 witness

2 years agosmt2: Make write port array stores conditional on nonzero write mask
Jannis Harder [Wed, 20 Apr 2022 15:49:48 +0000 (17:49 +0200)]
smt2: Make write port array stores conditional on nonzero write mask

2 years agoBump version
github-actions[bot] [Tue, 19 Apr 2022 00:14:02 +0000 (00:14 +0000)]
Bump version

2 years agoMerge pull request #3280 from YosysHQ/micko/fix_readaiw
Miodrag Milanović [Mon, 18 Apr 2022 07:49:21 +0000 (09:49 +0200)]
Merge pull request #3280 from YosysHQ/micko/fix_readaiw

Fix reading aiw from other solvers

2 years agoUpdate abc
Miodrag Milanovic [Mon, 18 Apr 2022 07:27:00 +0000 (09:27 +0200)]
Update abc

2 years agoverific: allow memories to be inferred in loops (vhdl)
Miodrag Milanovic [Mon, 18 Apr 2022 07:10:28 +0000 (09:10 +0200)]
verific: allow memories to be inferred in loops (vhdl)

2 years agoMerge pull request #3282 from nakengelhardt/verific_loop_rams
Miodrag Milanović [Mon, 18 Apr 2022 07:09:36 +0000 (09:09 +0200)]
Merge pull request #3282 from nakengelhardt/verific_loop_rams

verific: allow memories to be inferred in loops

2 years agoBump version
github-actions[bot] [Sat, 16 Apr 2022 00:14:57 +0000 (00:14 +0000)]
Bump version

2 years agomemory_share: Fix up mismatched address widths.
Marcelina Kościelnicka [Fri, 15 Apr 2022 13:05:08 +0000 (15:05 +0200)]
memory_share: Fix up mismatched address widths.

2 years agoopt_dff: Fix behavior on $ff with D == Q.
Marcelina Kościelnicka [Thu, 14 Apr 2022 13:08:20 +0000 (15:08 +0200)]
opt_dff: Fix behavior on $ff with D == Q.

2 years agoverific: allow memories to be inferred in loops
N. Engelhardt [Fri, 15 Apr 2022 13:10:48 +0000 (15:10 +0200)]
verific: allow memories to be inferred in loops

2 years agoFix reading aiw from other solvers
Miodrag Milanovic [Fri, 15 Apr 2022 09:45:16 +0000 (11:45 +0200)]
Fix reading aiw from other solvers

2 years agotribuf: `-formal` option: convert all to logic and detect conflicts
Jannis Harder [Tue, 29 Mar 2022 10:11:28 +0000 (12:11 +0200)]
tribuf: `-formal` option: convert all to logic and detect conflicts

2 years agoBump version
github-actions[bot] [Sat, 9 Apr 2022 00:15:22 +0000 (00:15 +0000)]
Bump version

2 years agoMerge pull request #3275 from YosysHQ/micko/clk2fflogic_fix
Miodrag Milanović [Fri, 8 Apr 2022 15:38:54 +0000 (17:38 +0200)]
Merge pull request #3275 from YosysHQ/micko/clk2fflogic_fix

Use wrap_async_control_gate if ff is fine

2 years agoUse wrap_async_control_gate if ff is fine
Miodrag Milanovic [Fri, 8 Apr 2022 14:30:29 +0000 (16:30 +0200)]
Use wrap_async_control_gate if ff is fine

2 years agoMerge pull request #3273 from modwizcode/fix-build
Miodrag Milanović [Fri, 8 Apr 2022 08:08:05 +0000 (10:08 +0200)]
Merge pull request #3273 from modwizcode/fix-build

Do not enable features that require the support of compression compiled in

2 years agopass jny: flipped the defaults for the inclusion of various bits of metadata
Aki Van Ness [Thu, 17 Mar 2022 11:26:14 +0000 (07:26 -0400)]
pass jny: flipped the defaults for the inclusion of various bits of metadata

2 years agopass jny: ensured the cell collection is cleared between modules
Aki Van Ness [Thu, 10 Mar 2022 16:05:04 +0000 (11:05 -0500)]
pass jny: ensured the cell collection is cleared between modules

2 years agopass jny: fixed missing quotes around the type value for the cell sort
Aki Van Ness [Thu, 10 Mar 2022 16:04:44 +0000 (11:04 -0500)]
pass jny: fixed missing quotes around the type value for the cell sort

2 years agopass jny: fixed the backslash escape for strings
Aki Van Ness [Thu, 10 Mar 2022 16:03:51 +0000 (11:03 -0500)]
pass jny: fixed the backslash escape for strings

2 years agopass jny: removed the invalid json escapes
Aki Van Ness [Thu, 24 Feb 2022 16:19:35 +0000 (11:19 -0500)]
pass jny: removed the invalid json escapes

2 years agopass jny: added some todo comments about things that need to be done before a proper...
Aki Van Ness [Thu, 24 Feb 2022 15:39:30 +0000 (10:39 -0500)]
pass jny: added some todo comments about things that need to be done before a proper merge, but it should be enough for the PoC at the moment

2 years agopass jny: changed the constructor initializers to use parens rather than curly-braces...
Aki Van Ness [Thu, 24 Feb 2022 14:54:03 +0000 (09:54 -0500)]
pass jny: changed the constructor initializers to use parens rather than curly-braces to hopefully make GCC 4.8 happy

2 years agopass jny: fixed the string escape method to be less jank and more proper
Aki Van Ness [Thu, 17 Feb 2022 16:35:45 +0000 (11:35 -0500)]
pass jny: fixed the string escape method to be less jank and more proper

2 years agopass jny: fixed the signed output for param value output
Aki Van Ness [Thu, 17 Feb 2022 13:15:48 +0000 (08:15 -0500)]
pass jny: fixed the signed output for param value output

2 years agopass jny: added connection output
Aki Van Ness [Thu, 17 Feb 2022 13:11:58 +0000 (08:11 -0500)]
pass jny: added connection output

2 years agopass jny: added filter options for including connections, attributes, and properties
Aki Van Ness [Thu, 10 Feb 2022 16:34:43 +0000 (11:34 -0500)]
pass jny: added filter options for including connections, attributes, and properties

2 years agopass jny: large chunk of refactoring to make the JSON output more pretty and the...
Aki Van Ness [Thu, 3 Feb 2022 10:04:45 +0000 (05:04 -0500)]
pass jny: large chunk of refactoring to make the JSON output more pretty and the internals less of a spaghetti nightmare

2 years agometadata -> jny: migrated to the proper name for the pass
Aki Van Ness [Fri, 14 Jan 2022 14:41:52 +0000 (09:41 -0500)]
metadata -> jny: migrated to the proper name for the pass

2 years agopass metadata: added the machinery to write param and attributes
Aki Van Ness [Fri, 3 Dec 2021 18:44:09 +0000 (13:44 -0500)]
pass metadata: added the machinery to write param and attributes

2 years agopass metadata: removed superfluous `stringf` calls
Aki Van Ness [Fri, 3 Dec 2021 18:43:11 +0000 (13:43 -0500)]
pass metadata: removed superfluous `stringf` calls

2 years agopass metadata: some more rough work on dumping the parameters and attributes
Aki Van Ness [Thu, 18 Nov 2021 12:35:14 +0000 (07:35 -0500)]
pass metadata: some more rough work on dumping the parameters and attributes

2 years agopass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy
Aki Van Ness [Thu, 18 Nov 2021 12:34:14 +0000 (07:34 -0500)]
pass metadata: fixed the MetadataWriter object initializer so GCC 4.8 is happy

2 years agopass metadata: added the output of parameters,
Aki Van Ness [Tue, 16 Nov 2021 20:25:14 +0000 (15:25 -0500)]
pass metadata: added the output of parameters,

it's kinda dumb at the moment and needs parsing based on type but it's a start

2 years agopass metadata: fixed some of the output formatting
Aki Van Ness [Tue, 16 Nov 2021 20:24:28 +0000 (15:24 -0500)]
pass metadata: fixed some of the output formatting

2 years agopass metadata: initial commit of the metadata pass for exporting design metadata...
Aki Van Ness [Tue, 16 Nov 2021 17:30:23 +0000 (12:30 -0500)]
pass metadata: initial commit of the metadata pass for exporting design metadata for yosys assisted tooling

2 years agoMakefile: properly conditionalize features requiring compression.
Iris Johnson [Fri, 8 Apr 2022 01:07:44 +0000 (20:07 -0500)]
Makefile: properly conditionalize features requiring compression.

2 years agoBump version
github-actions[bot] [Fri, 8 Apr 2022 00:15:41 +0000 (00:15 +0000)]
Bump version

2 years agoMerge pull request #3269 from YosysHQ/micko/fix_autotop
Catherine [Thu, 7 Apr 2022 22:40:35 +0000 (22:40 +0000)]
Merge pull request #3269 from YosysHQ/micko/fix_autotop

Reorder steps in -auto-top to fix synth command, fixes #3261

2 years agoabc: Add support for FFs with reset in -dff
Marcelina Kościelnicka [Thu, 7 Apr 2022 01:25:35 +0000 (03:25 +0200)]
abc: Add support for FFs with reset in -dff

2 years agoBump version
github-actions[bot] [Wed, 6 Apr 2022 00:14:30 +0000 (00:14 +0000)]
Bump version

2 years agosv: fix always_comb auto nosync for nested and function blocks
Zachary Snow [Tue, 22 Feb 2022 15:57:08 +0000 (16:57 +0100)]
sv: fix always_comb auto nosync for nested and function blocks

2 years agoReorder steps in -auto-top to fix synth command, fixes #3261
Miodrag Milanovic [Tue, 5 Apr 2022 12:02:37 +0000 (14:02 +0200)]
Reorder steps in -auto-top to fix synth command, fixes #3261

2 years agoNext dev cycle
Miodrag Milanovic [Tue, 5 Apr 2022 09:50:49 +0000 (11:50 +0200)]
Next dev cycle

2 years agoRelease version 0.16 yosys-0.16
Miodrag Milanovic [Tue, 5 Apr 2022 09:49:37 +0000 (11:49 +0200)]
Release version 0.16

2 years agoBump version
github-actions[bot] [Tue, 5 Apr 2022 00:13:50 +0000 (00:13 +0000)]
Bump version

2 years agoshow: Fix width labels.
Marcelina Kościelnicka [Mon, 4 Apr 2022 18:40:46 +0000 (20:40 +0200)]
show: Fix width labels.

See #3266.

2 years agoUpdate CHANGELOG and manual
Miodrag Milanovic [Mon, 4 Apr 2022 14:53:47 +0000 (16:53 +0200)]
Update CHANGELOG and manual

2 years agoMerge pull request #3265 from YosysHQ/micko/sim_improvements
Miodrag Milanović [Mon, 4 Apr 2022 07:56:56 +0000 (09:56 +0200)]
Merge pull request #3265 from YosysHQ/micko/sim_improvements

Improve sim by setting proper past D and AD signals

2 years agopast_ad initial value setting
Miodrag Milanovic [Sat, 2 Apr 2022 08:59:15 +0000 (10:59 +0200)]
past_ad initial value setting

2 years agosetInitState can be only one altering values
Miodrag Milanovic [Sat, 2 Apr 2022 08:34:11 +0000 (10:34 +0200)]
setInitState can be only one altering values

2 years agoSet past_d value for init state
Miodrag Milanovic [Sat, 2 Apr 2022 08:33:41 +0000 (10:33 +0200)]
Set past_d value for init state

2 years agoMerge pull request #3264 from jix/invalid_ff_dcinit_merge
Jannis Harder [Sat, 2 Apr 2022 10:41:28 +0000 (12:41 +0200)]
Merge pull request #3264 from jix/invalid_ff_dcinit_merge

opt_merge: Add `-keepdc` option required for formal verification

2 years agoBump version
github-actions[bot] [Sat, 2 Apr 2022 00:13:41 +0000 (00:13 +0000)]
Bump version

2 years agoopt_merge: Add `-keepdc` option required for formal verification
Jannis Harder [Fri, 1 Apr 2022 19:03:20 +0000 (21:03 +0200)]
opt_merge: Add `-keepdc` option required for formal verification

The `-keepdc` option prevents merging flipflops with dont-care bits in
their initial value, as, in general, this is not a valid transform for
formal verification.

The keepdc option of `opt` is passed along to `opt_merge` now.

2 years agoMerge pull request #3263 from YosysHQ/micko/clk2ff_init
Miodrag Milanović [Fri, 1 Apr 2022 17:37:02 +0000 (19:37 +0200)]
Merge pull request #3263 from YosysHQ/micko/clk2ff_init

Set init values for wrapped  async control signals

2 years agoSet init values for wrapped async control signals
Miodrag Milanovic [Fri, 1 Apr 2022 15:44:00 +0000 (17:44 +0200)]
Set init values for wrapped async control signals