From 00fccbf8dcf937e8c8e4b4b2cabf1e7658d8950f Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 9 Jun 2021 19:09:20 +0000 Subject: [PATCH] doh, should have reduced NC by 16 --- .../full_core_4_4ksram_litex_ls180_recon.v | 80 ++++++++----------- 1 file changed, 32 insertions(+), 48 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v index 782d303..2c8c54d 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v @@ -1,11 +1,13 @@ //-------------------------------------------------------------------------------- -// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 16:42:55 +// Auto-generated by Migen (7bc4eb1) & LiteX (35929c0f) on 2021-06-09 20:07:56 //-------------------------------------------------------------------------------- module ls180( - output wire spimaster_clk, - output wire spimaster_mosi, - output wire spimaster_cs_n, - input wire spimaster_miso, + input wire uart_tx, + input wire uart_rx, + output wire i2c_scl, + input wire i2c_sda_i, + output wire i2c_sda_o, + output wire i2c_sda_oe, output wire [12:0] sdram_a, input wire [15:0] sdram_dq_i, output wire [15:0] sdram_dq_o, @@ -18,18 +20,16 @@ module ls180( output wire [1:0] sdram_ba, output wire [1:0] sdram_dm, output wire sdram_clock, - input wire [15:0] gpio_i, - output wire [15:0] gpio_o, - output wire [15:0] gpio_oe, input wire eint_0, input wire eint_1, input wire eint_2, - output wire i2c_scl, - input wire i2c_sda_i, - output wire i2c_sda_o, - output wire i2c_sda_oe, - input wire uart_tx, - input wire uart_rx, + output wire spimaster_clk, + output wire spimaster_mosi, + output wire spimaster_cs_n, + input wire spimaster_miso, + input wire [15:0] gpio_i, + output wire [15:0] gpio_o, + output wire [15:0] gpio_oe, input wire sys_rst, input wire [1:0] sys_clksel_i, output wire sys_pll_testout_o, @@ -39,7 +39,7 @@ module ls180( input wire jtag_tck, input wire jtag_tdi, output wire jtag_tdo, - input wire [35:0] nc + input wire [19:0] nc ); (* ram_style = "distributed" *) reg main_libresocsim_reset_storage = 1'd0; @@ -160,10 +160,12 @@ wire main_libresocsim_libresoc_pll_vco_o; wire [1:0] main_libresocsim_libresoc_clk_sel; wire main_libresocsim_libresoc_pll_test_o; wire main_libresocsim_libresoc_pll_24_i; -reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; -reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; -wire main_libresocsim_libresoc_constraintmanager_spimaster_miso; +reg main_libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; +reg main_libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +wire main_libresocsim_libresoc_constraintmanager_i2c_scl; +wire main_libresocsim_libresoc_constraintmanager_i2c_sda_i; +wire main_libresocsim_libresoc_constraintmanager_i2c_sda_o; +wire main_libresocsim_libresoc_constraintmanager_i2c_sda_oe; reg [12:0] main_libresocsim_libresoc_constraintmanager_sdram_a = 13'd0; wire [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_i; reg [15:0] main_libresocsim_libresoc_constraintmanager_sdram_dq_o = 16'd0; @@ -176,18 +178,16 @@ reg main_libresocsim_libresoc_constraintmanager_sdram_cke = 1'd0; reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_ba = 2'd0; reg [1:0] main_libresocsim_libresoc_constraintmanager_sdram_dm = 2'd0; reg main_libresocsim_libresoc_constraintmanager_sdram_clock = 1'd0; -wire [15:0] main_libresocsim_libresoc_constraintmanager_gpio_i; -reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; -reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; wire main_libresocsim_libresoc_constraintmanager_eint_0; wire main_libresocsim_libresoc_constraintmanager_eint_1; wire main_libresocsim_libresoc_constraintmanager_eint_2; -wire main_libresocsim_libresoc_constraintmanager_i2c_scl; -wire main_libresocsim_libresoc_constraintmanager_i2c_sda_i; -wire main_libresocsim_libresoc_constraintmanager_i2c_sda_o; -wire main_libresocsim_libresoc_constraintmanager_i2c_sda_oe; -reg main_libresocsim_libresoc_constraintmanager_uart_tx = 1'd1; -reg main_libresocsim_libresoc_constraintmanager_uart_rx = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_clk = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_mosi = 1'd0; +reg main_libresocsim_libresoc_constraintmanager_spimaster_cs_n = 1'd0; +wire main_libresocsim_libresoc_constraintmanager_spimaster_miso; +wire [15:0] main_libresocsim_libresoc_constraintmanager_gpio_i; +reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_o = 16'd0; +reg [15:0] main_libresocsim_libresoc_constraintmanager_gpio_oe = 16'd0; reg [29:0] main_libresocsim_interface0_converted_interface_adr = 30'd0; reg [31:0] main_libresocsim_interface0_converted_interface_dat_w = 32'd0; wire [31:0] main_libresocsim_interface0_converted_interface_dat_r; @@ -1073,8 +1073,8 @@ reg [7:0] main_gpio1_pads_gpio1i = 8'd0; reg [7:0] main_gpio1_pads_gpio1o = 8'd0; reg [7:0] main_gpio1_pads_gpio1oe = 8'd0; reg [2:0] main_eint_tmp = 3'd0; -wire [35:0] main_nc; -reg [35:0] main_dummy = 36'd0; +wire [19:0] main_nc; +reg [19:0] main_dummy = 20'd0; wire main_i2c_scl; wire main_i2c_oe; wire main_i2c_sda0; @@ -3323,8 +3323,8 @@ assign builder_libresocsim_shared_err = (((((((((main_libresocsim_ram_bus_err | assign builder_libresocsim_wait = ((builder_libresocsim_shared_stb & builder_libresocsim_shared_cyc) & (~builder_libresocsim_shared_ack)); always @(*) begin builder_libresocsim_shared_ack <= 1'd0; - builder_libresocsim_shared_dat_r <= 32'd0; builder_libresocsim_error <= 1'd0; + builder_libresocsim_shared_dat_r <= 32'd0; builder_libresocsim_shared_ack <= (((((((((main_libresocsim_ram_bus_ack | main_ram_bus_ram_bus_ack) | main_libresocsim_libresoc_xics_icp_ack) | main_libresocsim_libresoc_xics_ics_ack) | main_interface0_converted_interface_ack) | main_interface1_converted_interface_ack) | main_interface2_converted_interface_ack) | main_interface3_converted_interface_ack) | main_wb_sdram_ack) | builder_libresocsim_libresocsim_wishbone_ack); builder_libresocsim_shared_dat_r <= (((((((((({32{builder_libresocsim_slave_sel_r[0]}} & main_libresocsim_ram_bus_dat_r) | ({32{builder_libresocsim_slave_sel_r[1]}} & main_ram_bus_ram_bus_dat_r)) | ({32{builder_libresocsim_slave_sel_r[2]}} & main_libresocsim_libresoc_xics_icp_dat_r)) | ({32{builder_libresocsim_slave_sel_r[3]}} & main_libresocsim_libresoc_xics_ics_dat_r)) | ({32{builder_libresocsim_slave_sel_r[4]}} & main_interface0_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[5]}} & main_interface1_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[6]}} & main_interface2_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[7]}} & main_interface3_converted_interface_dat_r)) | ({32{builder_libresocsim_slave_sel_r[8]}} & main_wb_sdram_dat_r)) | ({32{builder_libresocsim_slave_sel_r[9]}} & builder_libresocsim_libresocsim_wishbone_dat_r)); if (builder_libresocsim_done) begin @@ -4508,22 +4508,6 @@ always @(posedge sys_clk) begin main_dummy[17] <= (main_nc[17] | main_libresocsim_libresoc_interrupt[0]); main_dummy[18] <= (main_nc[18] | main_libresocsim_libresoc_interrupt[0]); main_dummy[19] <= (main_nc[19] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[20] <= (main_nc[20] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[21] <= (main_nc[21] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[22] <= (main_nc[22] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[23] <= (main_nc[23] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[24] <= (main_nc[24] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[25] <= (main_nc[25] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[26] <= (main_nc[26] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[27] <= (main_nc[27] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[28] <= (main_nc[28] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[29] <= (main_nc[29] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[30] <= (main_nc[30] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[31] <= (main_nc[31] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[32] <= (main_nc[32] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[33] <= (main_nc[33] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[34] <= (main_nc[34] | main_libresocsim_libresoc_interrupt[0]); - main_dummy[35] <= (main_nc[35] | main_libresocsim_libresoc_interrupt[0]); if ((main_libresocsim_interface0_converted_interface_ack | main_libresocsim_converter0_skip)) begin main_libresocsim_converter0_dat_r <= main_libresocsim_libresoc_ibus_dat_r; end @@ -5655,7 +5639,7 @@ always @(posedge sys_clk) begin main_gpio1_oe_re <= 1'd0; main_gpio1_out_storage <= 8'd0; main_gpio1_out_re <= 1'd0; - main_dummy <= 36'd0; + main_dummy <= 20'd0; main_i2c_storage <= 3'd0; main_i2c_re <= 1'd0; builder_subfragments_converter0_state <= 1'd0; -- 2.30.2