From 0628a53ddbc0d7913578895f5b3c5715b0016f76 Mon Sep 17 00:00:00 2001 From: Staf Verhaegen Date: Tue, 6 Apr 2021 20:32:12 +0200 Subject: [PATCH] Add sim models for SRAM block. Both Verilog and VHDL model is provided. --- ls180/SPBlock_512W64B8W.v | 35 +++++++++++++++++++++++++ ls180/SPBlock_512W64B8W.vhdl | 50 ++++++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 ls180/SPBlock_512W64B8W.v create mode 100644 ls180/SPBlock_512W64B8W.vhdl diff --git a/ls180/SPBlock_512W64B8W.v b/ls180/SPBlock_512W64B8W.v new file mode 100644 index 0000000..2188fd4 --- /dev/null +++ b/ls180/SPBlock_512W64B8W.v @@ -0,0 +1,35 @@ +// SPBlock_512W64B8W simulation mode +module SPBlock_512W64B8W( + input clk, + input [8:0] a, + input [63:0] d, + output [63:0] q, + // Width of WE determines the write granularity + input [7:0] we +); + +genvar i; + +reg [63:0] ram [511:0]; +wire[7:0] d_split [7:0]; +reg [8:0] a_hold; + +always @(posedge clk) begin + a_hold <= a; +end + +assign q = ram[a_hold]; + +generate + for (i = 0; i < 8; i = i + 1) begin + assign d_split[i] = d[((i + 1)*8 - 1):i*8]; + + always @(posedge clk) begin + if (we[i]) begin + ram[a][((i + 1)*8 - 1):i*8] = d_split[i]; + end + end + end +endgenerate + +endmodule diff --git a/ls180/SPBlock_512W64B8W.vhdl b/ls180/SPBlock_512W64B8W.vhdl new file mode 100644 index 0000000..8887d98 --- /dev/null +++ b/ls180/SPBlock_512W64B8W.vhdl @@ -0,0 +1,50 @@ +-- SPBlock_512W64B8W simulation model +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity SPBlock_512W64B8W is +port ( + CLK: in std_logic; + A: in std_logic_vector(8 downto 0); + D: in std_logic_vector(63 downto 0); + Q: out std_logic_vector(63 downto 0); + -- Width of WE determines the write granularity + WE: in std_logic_vector(7 downto 0) +); +end entity SPBlock_512W64B8W; + +architecture rtl of SPBlock_512W64B8W is + constant WORDS: integer := 512; + constant WEBITS: integer := WE'length; + constant WEWORDBITS: integer := 8; + type word is array (WEBITS - 1 downto 0) of std_logic_vector(WEWORDBITS - 1 downto 0); + type ram_type is array (0 to WORDS - 1) of word; + + signal RAM: ram_type; + signal A_hold: std_logic_vector(A'range); + + signal addr: integer; + signal addr_hold: integer; + begin + addr <= to_integer(unsigned(A)); + addr_hold <= to_integer(unsigned(A_hold)); + + process(CLK) is + begin + if (rising_edge(CLK)) then + A_hold <= A; + for weword in 0 to WEBITS - 1 loop + if WE(weword) = '1' then + -- Write cycle + RAM(addr)(weword) <= D((weword + 1)*WEWORDBITS - 1 downto weword*WEWORDBITS); + end if; + end loop; + end if; + end process; + + read: for weword in 0 to WE'length - 1 generate + begin + Q((weword + 1)*WEWORDBITS - 1 downto weword*WEWORDBITS) <= RAM(addr_hold)(weword); + end generate; +end architecture rtl; -- 2.30.2