From 1019f57e6e49ae45d27296f21e1157b40ef06160 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 10:08:06 +0100 Subject: [PATCH] AddingPeripherals.mdwn --- docs/AddingPeripherals.mdwn | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn index e905a4a..2ad2929 100644 --- a/docs/AddingPeripherals.mdwn +++ b/docs/AddingPeripherals.mdwn @@ -75,7 +75,7 @@ the address lines to 13-bit wide: def sdram3(suffix, bank): buspins = [] - inout = [] + inout = [] for i in range(12, 13): buspins.append("SDRAD%d+" % i) for i in range(8, 64): @@ -215,7 +215,7 @@ The first requirement is that the pins from the peripheral side be connected through to IO cells. This can be verified by running the pinmux code generator (to activate "default" behaviour), just to see what happens: - $ python src/pinmux_generator.py -o i_class + $ python src/pinmux_generator.py -o i_class Files are auto-generated in ./i\_class/bsv\_src and it is recommended to examine the pinmux.bsv file in an editor, and search for occurrences @@ -446,8 +446,6 @@ removed from the template: interface sdram_out=sdram.ifc_sdram_out; <--- xxxx `endif <--- xxxx - - Next, again searching for signs of the "hand-written" code, we encounter the fabric connectivity, which wires the SDRAM to the AXI4. We note however that there is not just one AXI slave device but *two*: one for the SDRAM -- 2.30.2