From 16a98a363bc6261c66ba122f1637aaa0be3c7ec8 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Jean-Fran=C3=A7ois=20Nguyen?= Date: Mon, 28 Jun 2021 15:42:45 +0200 Subject: [PATCH] test: move to sim = Simulator(dut) instead of context manager. --- lambdasoc/test/test_periph_base.py | 7 ++++--- lambdasoc/test/test_periph_event.py | 7 ++++--- lambdasoc/test/test_periph_intc.py | 5 +++-- lambdasoc/test/test_periph_serial.py | 7 ++++--- lambdasoc/test/test_periph_sram.py | 7 ++++--- lambdasoc/test/test_periph_timer.py | 7 ++++--- 6 files changed, 23 insertions(+), 17 deletions(-) diff --git a/lambdasoc/test/test_periph_base.py b/lambdasoc/test/test_periph_base.py index 925f49d..c3f59ff 100644 --- a/lambdasoc/test/test_periph_base.py +++ b/lambdasoc/test/test_periph_base.py @@ -9,9 +9,10 @@ from ..periph.base import Peripheral, CSRBank, PeripheralBridge def simulation_test(dut, process): - with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim: - sim.add_clock(1e-6) - sim.add_sync_process(process) + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(process) + with sim.write_vcd("test.vcd"): sim.run() diff --git a/lambdasoc/test/test_periph_event.py b/lambdasoc/test/test_periph_event.py index 69aacf2..4dfea23 100644 --- a/lambdasoc/test/test_periph_event.py +++ b/lambdasoc/test/test_periph_event.py @@ -8,9 +8,10 @@ from ..periph.event import * def simulation_test(dut, process): - with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim: - sim.add_clock(1e-6) - sim.add_sync_process(process) + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(process) + with sim.write_vcd("test.vcd"): sim.run() diff --git a/lambdasoc/test/test_periph_intc.py b/lambdasoc/test/test_periph_intc.py index add61e9..6aa2f0d 100644 --- a/lambdasoc/test/test_periph_intc.py +++ b/lambdasoc/test/test_periph_intc.py @@ -103,6 +103,7 @@ class GenericInterruptControllerTestCase(unittest.TestCase): yield Delay(1e-6) self.assertEqual((yield dut.ip), 0b11) - with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim: - sim.add_process(process) + sim = Simulator(dut) + sim.add_process(process) + with sim.write_vcd("test.vcd"): sim.run() diff --git a/lambdasoc/test/test_periph_serial.py b/lambdasoc/test/test_periph_serial.py index 48bc126..e73c274 100644 --- a/lambdasoc/test/test_periph_serial.py +++ b/lambdasoc/test/test_periph_serial.py @@ -51,7 +51,8 @@ class AsyncSerialPeripheralTestCase(unittest.TestCase): self.assertEqual(rx_data, 0xab) yield - with Simulator(m, vcd_file=open("test.vcd", "w")) as sim: - sim.add_clock(1e-6) - sim.add_sync_process(process) + sim = Simulator(m) + sim.add_clock(1e-6) + sim.add_sync_process(process) + with sim.write_vcd("test.vcd"): sim.run() diff --git a/lambdasoc/test/test_periph_sram.py b/lambdasoc/test/test_periph_sram.py index 7e4b95e..266de6d 100644 --- a/lambdasoc/test/test_periph_sram.py +++ b/lambdasoc/test/test_periph_sram.py @@ -13,9 +13,10 @@ from ..periph.sram import SRAMPeripheral def simulation_test(dut, process): - with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim: - sim.add_clock(1e-6) - sim.add_sync_process(process) + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(process) + with sim.write_vcd("test.vcd"): sim.run() diff --git a/lambdasoc/test/test_periph_timer.py b/lambdasoc/test/test_periph_timer.py index 21a406a..cdbb998 100644 --- a/lambdasoc/test/test_periph_timer.py +++ b/lambdasoc/test/test_periph_timer.py @@ -10,9 +10,10 @@ from ..periph.timer import TimerPeripheral def simulation_test(dut, process): - with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim: - sim.add_clock(1e-6) - sim.add_sync_process(process) + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(process) + with sim.write_vcd("test.vcd"): sim.run() -- 2.30.2