From 1b176822349c1f6c828e0156534e2f4d42e1841e Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 15 Apr 2022 18:44:27 +0200 Subject: [PATCH] whitespace --- src/ls2.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ls2.py b/src/ls2.py index d953350..cc55d19 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -283,7 +283,8 @@ class DDR3SoC(SoC, Elaboratable): # set up clock request generator pod_bits = 25 - if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s', 'orangecrab']: + if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s', + 'orangecrab']: if fpga in ['isim']: pod_bits = 6 self.crg = ECP5CRG(clk_freq, dram_clk_freq=None, pod_bits=pod_bits) -- 2.30.2