From 1d8980a07b9d868b654af694dd7bfcd1ebed46a1 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Mon, 31 Oct 2022 17:43:15 -0700 Subject: [PATCH] change Op/Ty/SSAVal reprs to be easier to read --- .../_tests/test_compiler_ir2.py | 168 +++++------------- src/bigint_presentation_code/compiler_ir2.py | 33 +++- 2 files changed, 76 insertions(+), 125 deletions(-) diff --git a/src/bigint_presentation_code/_tests/test_compiler_ir2.py b/src/bigint_presentation_code/_tests/test_compiler_ir2.py index be7f69f..dfa43e6 100644 --- a/src/bigint_presentation_code/_tests/test_compiler_ir2.py +++ b/src/bigint_presentation_code/_tests/test_compiler_ir2.py @@ -1,13 +1,15 @@ import unittest -from bigint_presentation_code.compiler_ir import GPR_SIZE_IN_BYTES -from bigint_presentation_code.compiler_ir2 import (Fn, OpKind, PreRASimState) +from bigint_presentation_code.compiler_ir2 import (GPR_SIZE_IN_BYTES, Fn, + OpKind, PreRASimState, + SSAVal) class TestCompilerIR(unittest.TestCase): maxDiff = None - def test_sim(self): + def make_add_fn(self): + # type: () -> tuple[Fn, SSAVal] fn = Fn() op0 = fn.append_new_op(OpKind.FuncArgR3, name="arg") arg = op0.outputs[0] @@ -29,121 +31,43 @@ class TestCompilerIR(unittest.TestCase): fn.append_new_op( OpKind.SvStd, inputs=[s, arg, vl], immediates=[0], maxvl=MAXVL, name="st") + return fn, arg + def test_repr(self): + fn, _arg = self.make_add_fn() self.assertEqual([repr(i) for i in fn.ops], [ - "Op(fn=, properties=OpProperties(kind=OpKind.FuncArgR3, " - "inputs=(), outputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet([3])}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=1)), " - "tied_input_index=None, spread_index=None),), maxvl=1), " - "inputs=OpInputs([], op=...), " - "immediates=OpImmediates([], op=...), " - "outputs=(,), " - "name='arg')", - "Op(fn=, properties=OpProperties(kind=OpKind.SetVLI, " - "inputs=(), outputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.VL_MAXVL: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), " - "tied_input_index=None, spread_index=None),), maxvl=1), " - "inputs=OpInputs([], op=...), " - "immediates=OpImmediates([32], op=...), " - "outputs=(,), " - "name='vl')", - "Op(fn=, properties=OpProperties(kind=OpKind.SvLd, " - "inputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=1)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.VL_MAXVL: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), " - "tied_input_index=None, spread_index=None)), " - "outputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet(range(14, 97))}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), " - "tied_input_index=None, spread_index=None),), maxvl=32), " - "inputs=OpInputs([, ], op=...), " - "immediates=OpImmediates([0], op=...), " - "outputs=(,), " - "name='ld')", - "Op(fn=, properties=OpProperties(kind=OpKind.SvLI, " - "inputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.VL_MAXVL: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), " - "tied_input_index=None, spread_index=None),), outputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet(range(14, 97))}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), " - "tied_input_index=None, spread_index=None),), maxvl=32), " - "inputs=OpInputs([], op=...), " - "immediates=OpImmediates([0], op=...), " - "outputs=(,), " - "name='li')", - "Op(fn=, properties=OpProperties(kind=OpKind.SetCA, " - "inputs=(), outputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.CA: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.CA, reg_len=1)), " - "tied_input_index=None, spread_index=None),), maxvl=1), " - "inputs=OpInputs([], op=...), " - "immediates=OpImmediates([], op=...), " - "outputs=(,), " - "name='ca')", - "Op(fn=, properties=OpProperties(kind=OpKind.SvAddE, " - "inputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet(range(14, 97))}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet(range(14, 97))}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.CA: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.CA, reg_len=1)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.VL_MAXVL: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), " - "tied_input_index=None, spread_index=None)), outputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet(range(14, 97))}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.CA: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.CA, reg_len=1)), " - "tied_input_index=None, spread_index=None)), maxvl=32), " - "inputs=OpInputs([, , , ], op=...), " - "immediates=OpImmediates([], op=...), " - "outputs=(, ), " - "name='add')", - "Op(fn=, properties=OpProperties(kind=OpKind.SvStd, " - "inputs=(" - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet(range(14, 97))}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=32)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.GPR: FBitSet([*range(3, 13), *range(14, 128)])}), " - "ty=Ty(base_ty=BaseTy.I64, reg_len=1)), " - "tied_input_index=None, spread_index=None), " - "OperandDesc(loc_set_before_spread=LocSet(starts=FMap({" - "LocKind.VL_MAXVL: FBitSet([0])}), " - "ty=Ty(base_ty=BaseTy.VL_MAXVL, reg_len=1)), " - "tied_input_index=None, spread_index=None)), " - "outputs=(), maxvl=32), " - "inputs=OpInputs([, , ], op=...), " - "immediates=OpImmediates([0], op=...), outputs=(), " - "name='st')", + "Op(kind=OpKind.FuncArgR3, " + "inputs=[], " + "immediates=[], " + "outputs=(>,), name='arg')", + "Op(kind=OpKind.SetVLI, " + "inputs=[], " + "immediates=[32], " + "outputs=(>,), name='vl')", + "Op(kind=OpKind.SvLd, " + "inputs=[>, >], " + "immediates=[0], " + "outputs=(>,), name='ld')", + "Op(kind=OpKind.SvLI, " + "inputs=[>], " + "immediates=[0], " + "outputs=(>,), name='li')", + "Op(kind=OpKind.SetCA, " + "inputs=[], " + "immediates=[], " + "outputs=(>,), name='ca')", + "Op(kind=OpKind.SvAddE, " + "inputs=[>, >, >, >], " + "immediates=[], " + "outputs=(>, >), name='add')", + "Op(kind=OpKind.SvStd, " + "inputs=[>, >, >], " + "immediates=[0], " + "outputs=(), name='st')", ]) + def test_sim(self): + fn, arg = self.make_add_fn() addr = 0x100 state = PreRASimState(ssa_vals={arg: (addr,)}, memory={}) state.store(addr=addr, value=0xffffffff_ffffffff, @@ -152,16 +76,16 @@ class TestCompilerIR(unittest.TestCase): size_in_bytes=GPR_SIZE_IN_BYTES) self.assertEqual( repr(state), - "PreRASimState(ssa_vals={: (0x100,)}, memory={\n" + "PreRASimState(ssa_vals={>: (0x100,)}, memory={\n" "0x00100: <0xffffffffffffffff>,\n" "0x00108: <0xabcdef0123456789>})") fn.pre_ra_sim(state) self.assertEqual( repr(state), "PreRASimState(ssa_vals={\n" - ": (0x100,),\n" - ": (0x20,),\n" - ": (\n" + ">: (0x100,),\n" + ">: (0x20,),\n" + ">: (\n" " 0xffffffffffffffff, 0xabcdef0123456789, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" @@ -170,7 +94,7 @@ class TestCompilerIR(unittest.TestCase): " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0),\n" - ": (\n" + ">: (\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" @@ -179,8 +103,8 @@ class TestCompilerIR(unittest.TestCase): " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0),\n" - ": (0x1,),\n" - ": (\n" + ">: (0x1,),\n" + ">: (\n" " 0x0, 0xabcdef012345678a, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" @@ -189,7 +113,7 @@ class TestCompilerIR(unittest.TestCase): " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0,\n" " 0x0, 0x0, 0x0, 0x0),\n" - ": (0x0,),\n" + ">: (0x0,),\n" "}, memory={\n" "0x00100: <0x0000000000000000>,\n" "0x00108: <0xabcdef012345678a>,\n" diff --git a/src/bigint_presentation_code/compiler_ir2.py b/src/bigint_presentation_code/compiler_ir2.py index 00e6221..e6ffe4e 100644 --- a/src/bigint_presentation_code/compiler_ir2.py +++ b/src/bigint_presentation_code/compiler_ir2.py @@ -88,7 +88,7 @@ class BaseTy(Enum): return "BaseTy." + self._name_ -@plain_data(frozen=True, unsafe_hash=True) +@plain_data(frozen=True, unsafe_hash=True, repr=False) @final class Ty: __slots__ = "base_ty", "reg_len" @@ -113,6 +113,14 @@ class Ty: self.base_ty = base_ty self.reg_len = reg_len + def __repr__(self): + # type: () -> str + if self.reg_len != 1: + reg_len = f"*{self.reg_len}" + else: + reg_len = "" + return f"<{self.base_ty._name_}{reg_len}>" + @unique @final @@ -1030,7 +1038,7 @@ class SSAVal: def __repr__(self): # type: () -> str - return f"<{self.op.name}#{self.output_idx}>" + return f"<{self.op.name}#{self.output_idx}: {self.ty}>" @cached_property def defining_descriptor(self): @@ -1181,7 +1189,7 @@ class OpImmediates(OpInputSeq[int, range]): super().__init__(items, op) -@plain_data(frozen=True, eq=False) +@plain_data(frozen=True, eq=False, repr=False) @final class Op: __slots__ = "fn", "properties", "inputs", "immediates", "outputs", "name" @@ -1209,6 +1217,25 @@ class Op: def __hash__(self): return object.__hash__(self) + def __repr__(self): + # type: () -> str + field_vals = [] # type: list[str] + for name in fields(self): + if name == "properties": + name = "kind" + elif name == "fn": + continue + try: + value = getattr(self, name) + except AttributeError: + field_vals.append(f"{name}=") + continue + if isinstance(value, OpInputSeq): + value = list(value) # type: ignore + field_vals.append(f"{name}={value!r}") + field_vals_str = ", ".join(field_vals) + return f"Op({field_vals_str})" + def pre_ra_sim(self, state): # type: (PreRASimState) -> None for inp in self.inputs: -- 2.30.2