From 1fed7eb28605c7498cd44672ebae37eae2a96ac7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 10 Apr 2022 18:15:35 +0100 Subject: [PATCH] Revert "Wire up missing CRG / DDR3 clock control / reset signals" This reverts commit 19ed0026e91b2dd351fbd2d692fb2c6f45b42622. --- src/ecp5_crg.py | 24 ++++++++++-------------- src/ls2.py | 4 ---- 2 files changed, 10 insertions(+), 18 deletions(-) diff --git a/src/ecp5_crg.py b/src/ecp5_crg.py index 86358d4..5c975d6 100644 --- a/src/ecp5_crg.py +++ b/src/ecp5_crg.py @@ -173,10 +173,6 @@ class ECP5CRG(Elaboratable): self.sys_clk_freq = sys_clk_freq self.pod_bits = pod_bits - # DDR clock control signals - self.ddr_clk_stop = Signal() - self.ddr_clk_reset = Signal() - def elaborate(self, platform): m = Module() @@ -208,18 +204,18 @@ class ECP5CRG(Elaboratable): i_GSR=gsr1), ] - # Power-on delay + # PLL + m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~reset) + + # Power-on delay (655us) podcnt = Signal(self.pod_bits, reset=-1) pod_done = Signal() - with m.If(podcnt != 0): + with m.If((podcnt != 0) & pll.locked): m.d.rawclk += podcnt.eq(podcnt-1) m.d.rawclk += pod_done.eq(podcnt == 0) - # PLL - m.submodules.pll = pll = PLL(ClockSignal("rawclk"), reset=~pod_done|~reset) - # Generating sync2x (200Mhz) and init (25Mhz) from extclk - cd_sync2x = ClockDomain("sync2x", local=False, reset_less=True) + cd_sync2x = ClockDomain("sync2x", local=False) cd_sync2x_unbuf = ClockDomain("sync2x_unbuf", local=False, reset_less=True) cd_init = ClockDomain("init", local=False) @@ -232,7 +228,7 @@ class ECP5CRG(Elaboratable): pll.create_clkout(ClockSignal("init"), 25e6) m.submodules += Instance("ECLKSYNCB", i_ECLKI = ClockSignal("sync2x_unbuf"), - i_STOP = self.ddr_clk_stop, + i_STOP = 0, o_ECLKO = ClockSignal("sync2x")) m.domains += cd_sync2x_unbuf m.domains += cd_sync2x @@ -242,8 +238,8 @@ class ECP5CRG(Elaboratable): reset_ok = Signal(reset_less=True) m.d.comb += reset_ok.eq(~pll.locked|~pod_done) m.d.comb += ResetSignal("init").eq(reset_ok) - m.d.comb += ResetSignal("sync").eq(reset_ok|self.ddr_clk_reset) - m.d.comb += ResetSignal("dramsync").eq(reset_ok|self.ddr_clk_reset) + m.d.comb += ResetSignal("sync").eq(reset_ok) + m.d.comb += ResetSignal("dramsync").eq(reset_ok) # # Generating sync (100Mhz) from sync2x @@ -251,7 +247,7 @@ class ECP5CRG(Elaboratable): p_DIV="2.0", i_ALIGNWD=0, i_CLKI=ClockSignal("sync2x"), - i_RST=ResetSignal("dramsync"), + i_RST=0, o_CDIVX=ClockSignal("sync")) # temporarily set dram sync clock exactly equal to main sync diff --git a/src/ls2.py b/src/ls2.py index 3909b8a..1e0ca44 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -518,10 +518,6 @@ class DDR3SoC(SoC, Elaboratable): # grrr, same problem with drambone: not WB4-pipe compliant comb += drambone.bus.stall.eq(drambone.bus.cyc & ~drambone.bus.ack) - # DRAM clock control / reset signals - comb += self.crg.ddr_clk_stop.eq(self.ddrphy.init.stop) - comb += self.crg.ddr_clk_reset.eq(self.ddrphy.init.reset) - # add hyperram module if hasattr(self, "hyperram"): m.submodules.hyperram = hyperram = self.hyperram -- 2.30.2