From 21924054a7c9ca826d0fc047bb1501dfda425506 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 1 Aug 2018 08:40:45 +0100 Subject: [PATCH] AddingPeripherals.mdwn --- docs/AddingPeripherals.mdwn | 3 ++- src/bsv/peripheral_gen/sdram.py | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/docs/AddingPeripherals.mdwn b/docs/AddingPeripherals.mdwn index 2c04d29..1f46b46 100644 --- a/docs/AddingPeripherals.mdwn +++ b/docs/AddingPeripherals.mdwn @@ -285,7 +285,8 @@ is added. So first, we must identify the nearest similar class. FlexBus looks like a good candidate, so we take a copy of src/bsv/peripheral\_gen/flexbus.py called sdram.py. The simplest next step is to global/search/replace -"flexbus" with "sdram". At this phase, despite knowing that it will +"flexbus" with "sdram", and for peripheral instance declaration replace +"fb" with "sdr". At this phase, despite knowing that it will auto-generate the wrong code, we add it as a "supported" peripheral at the bottom of src/bsv/peripheral\_gen/base.py, in the "PFactory" (Peripheral Factory) class: diff --git a/src/bsv/peripheral_gen/sdram.py b/src/bsv/peripheral_gen/sdram.py index baf355d..b676933 100644 --- a/src/bsv/peripheral_gen/sdram.py +++ b/src/bsv/peripheral_gen/sdram.py @@ -14,7 +14,7 @@ class sdram(PBase): ".sdram_side") def fastifdecl(self, name, count): - return "//interface FlexBus_Master_IFC fb{0}_out;".format(count) + return "//interface FlexBus_Master_IFC sdr{0}_out;".format(count) def get_clock_reset(self, name, count): return "slow_clock, slow_reset" @@ -22,10 +22,10 @@ class sdram(PBase): def mkfast_peripheral(self): return "AXI4_Slave_to_FlexBus_Master_Xactor_IFC " + \ "#(`PADDR, `DATA, `USERSPACE)\n" + \ - " fb{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;" + " sdr{0} <- mkAXI4_Slave_to_FlexBus_Master_Xactor;" def _mk_connection(self, name=None, count=0): - return "fb{0}.axi_side" + return "sdr{0}.axi_side" def pinname_in(self, pname): return {'ta': 'sdram_side.m_tAn', -- 2.30.2