From 24cbbcc90272b20d96eda94266bf8f4c980501d3 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 3 Jun 2021 21:52:45 +0000 Subject: [PATCH] rename sys_clk to sys_clk_0 and rename ref_clk to sys_clk this restores ls180 module to minimise changes --- .../full_core_4_4ksram_litex_ls180_recon.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v index 364dcc5..d96c035 100644 --- a/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v +++ b/experiments9/non_generated/full_core_4_4ksram_litex_ls180_recon.v @@ -30,7 +30,7 @@ module ls180( input wire i2c_sda_i, output wire i2c_sda_o, output wire i2c_sda_oe, - input wire ref_clk, + input wire sys_clk, input wire sys_rst, input wire [1:0] sys_clksel_i, output wire sys_pll_testout_o, @@ -42,7 +42,7 @@ module ls180( input wire [35:0] nc ); -wire sys_clk; +wire sys_clk_0; (* ram_style = "distributed" *) reg libresocsim_reset_storage = 1'd0; reg libresocsim_reset_re = 1'd0; (* ram_style = "distributed" *) reg [31:0] libresocsim_scratch_storage = 32'd305419896; @@ -1865,8 +1865,8 @@ end assign ram_adr = ram_bus_ram_bus_adr[4:0]; assign ram_bus_ram_bus_dat_r = ram_dat_r; assign ram_dat_w = ram_bus_ram_bus_dat_w; -assign sys_clk_1 = sys_clk; -assign por_clk = sys_clk; +assign sys_clk_1 = sys_clk_0; +assign por_clk = sys_clk_0; assign sys_rst_1 = int_rst; assign dfi_p0_address = sdram_master_p0_address; assign dfi_p0_bank = sdram_master_p0_bank; @@ -5814,7 +5814,7 @@ test_issuer test_issuer( .TAP_bus__tdi(libresocsim_libresoc_jtag_tdi), .TAP_bus__tms(libresocsim_libresoc_jtag_tms), .clk(sys_clk_1), - .ref_clk(ref_clk), + .ref_clk(sys_clk), .clk_sel_i(libresocsim_libresoc_clk_sel), .core_bigendian_i(1'd0), .dbus__ack(libresocsim_libresoc_dbus_ack), @@ -6089,7 +6089,7 @@ test_issuer test_issuer( .pc_o(libresocsim_libresoc3), .pll_test_o(libresocsim_libresoc_pll_test_o), .pll_vco_o(libresocsim_libresoc_pll_vco_o), - .pllclk_clk(sys_clk), + .pllclk_clk(sys_clk_0), .sdr_a_0__pad__o(sdram_a[0]), .sdr_a_10__pad__o(sdram_a[10]), .sdr_a_11__pad__o(sdram_a[11]), -- 2.30.2