From 2862424f08cfdd4efc5ac80392a961a52a7c1cb0 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Mon, 8 Nov 2021 21:02:07 +0100 Subject: [PATCH] mmu unit test working again --- src/soc/fu/mmu/fsm.py | 3 ++- src/soc/simple/test/test_issuer_mmu.py | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py index 78969252..e6345df7 100644 --- a/src/soc/fu/mmu/fsm.py +++ b/src/soc/fu/mmu/fsm.py @@ -165,7 +165,8 @@ class FSMMMUStage(ControlBase): comb += done.eq(1) # FIXME l_out.done with m.Case(MicrOp.OP_MFSPR): - comb += Display("MMUTEST: OP_MFSPR: spr=%i",spr); + comb += Display("MMUTEST: OP_MFSPR: spr=%i returns=%i", + spr,spr1_i); comb += o.data.eq(spr1_i) comb += o.ok.eq(1) comb += done.eq(1) diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py index e8f14b25..d377e935 100644 --- a/src/soc/simple/test/test_issuer_mmu.py +++ b/src/soc/simple/test/test_issuer_mmu.py @@ -54,7 +54,7 @@ class MMUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - # BROKEN - missing expected Display output + # OP_MTSPR: spr=720 def case_3_mtspr(self): lst = ["mtspr 720,1"] # mtspr PRTBL,r1 initial_regs = [0] * 32 @@ -63,7 +63,7 @@ class MMUTestCase(TestAccumulatorBase): self.add_case(Program(lst, bigendian), initial_regs, initial_mem=initial_mem) - # BROKEN - missing expected Display output + # OP_MFSPR: spr=18/19 def case_4_mfspr(self): lst = ["mfspr 1,18", # mtspr r1,DSISR "mfspr 2,19"] # mtspr r2,DAR -- 2.30.2