From 2aa0ebe16f0c05518d8ddff34d8f1ce00eac8ad6 Mon Sep 17 00:00:00 2001 From: Cesar Strauss Date: Wed, 21 Apr 2021 16:42:56 -0300 Subject: [PATCH] CR sub-fields are stored in MSB0 order --- src/soc/consts.py | 18 ++++++++++++++++++ src/soc/simple/issuer.py | 17 +++++++++-------- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/src/soc/consts.py b/src/soc/consts.py index 9b43a4b0..3060c826 100644 --- a/src/soc/consts.py +++ b/src/soc/consts.py @@ -254,3 +254,21 @@ botchify(SVP64MODEb, SVP64MODE, SVP64MODE_SIZE-1) # add subfields to use with nmutil.sel SVP64MODE.MOD2 = [0, 1] SVP64MODE.CR = [3, 4] + + +# CR sub-fields +class CRb: + LT = 0 + GT = 1 + EQ = 2 + SO = 3 + + +CR_SIZE = 4 + + +class CR: + pass + + +botchify(CRb, CR, CR_SIZE-1) diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py index 66321857..fa019d4c 100644 --- a/src/soc/simple/issuer.py +++ b/src/soc/simple/issuer.py @@ -34,6 +34,7 @@ from soc.config.test.test_loadstore import TestMemPspec from soc.config.ifetch import ConfigFetchUnit from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR, SVP64PredMode) +from soc.consts import CR from soc.debug.dmi import CoreDebug, DMIInterface from soc.debug.jtag import JTAG from soc.config.pinouts import get_pinspecs @@ -123,28 +124,28 @@ def get_predcr(m, mask, name): invert = Signal(name=name+"crinvert") with m.Switch(mask): with m.Case(SVP64PredCR.LT.value): - comb += idx.eq(0) + comb += idx.eq(CR.LT) comb += invert.eq(0) with m.Case(SVP64PredCR.GE.value): - comb += idx.eq(0) + comb += idx.eq(CR.LT) comb += invert.eq(1) with m.Case(SVP64PredCR.GT.value): - comb += idx.eq(1) + comb += idx.eq(CR.GT) comb += invert.eq(0) with m.Case(SVP64PredCR.LE.value): - comb += idx.eq(1) + comb += idx.eq(CR.GT) comb += invert.eq(1) with m.Case(SVP64PredCR.EQ.value): - comb += idx.eq(2) + comb += idx.eq(CR.EQ) comb += invert.eq(0) with m.Case(SVP64PredCR.NE.value): - comb += idx.eq(1) + comb += idx.eq(CR.EQ) comb += invert.eq(1) with m.Case(SVP64PredCR.SO.value): - comb += idx.eq(3) + comb += idx.eq(CR.SO) comb += invert.eq(0) with m.Case(SVP64PredCR.NS.value): - comb += idx.eq(3) + comb += idx.eq(CR.SO) comb += invert.eq(1) return idx, invert -- 2.30.2