From 362b54b6e73894ccca070f53cee4b5817cf3b47f Mon Sep 17 00:00:00 2001 From: Aleksandar Kostovic Date: Thu, 14 Feb 2019 10:16:54 +0100 Subject: [PATCH] Turned the normalise_2 verilog state into nmigen --- src/add/nmigen_add_experiment.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index c197d735..df100d1c 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -251,6 +251,20 @@ class FPADD: round_bit.eq(tot[1]), sticky.eq(tot[0]) ] + + with m.State("normalise_2"): + with m.If(z_e < -126): + m.d.sync +=[ + z_e.eq(z_e + 1), + z_m.eq(z_m >> 1), + guard.eq(z_m[0]), + round_bit.eq(guard), + sticky.eq(sticky | round_bit) + ] + + with m.Else(): + m.next = "round" + return m """ -- 2.30.2